Real time storage/retrieval subsystem for document processing in banking operations

ABSTRACT

A storage/retrieval module apparatus for use in a document imaging system can receive digitized optical image and related information data, convert it to electrical digital data for storage on disk at high rates of speed. Concurrently with storage operations, the storage/retrieval module apparatus can also execute retrieval of stored data under command of a host computer or a connected workstation.

This is a continuation of co-pending application Ser. No. 07/419,566filed on Oct. 10, 1989 now abandoned.

FIELD OF THE INVENTION

This disclosure relates to storage and retrieval methods and systemsusable for high speed, high volume data storage/retrieval and imagestorage/retrieval operations.

CROSS REFERENCES TO RELATED APPLICATIONS

This disclosure relates to a co-pending application filed on the samedate as this application and which issued as U.S. Pat. No. 5,170,466 onDec. 8, 1992 with the title "Storage/Retrieval System for Document".This patent involved a high-speed storage/retrieval system for storageand retrieval of digital document images which permitted clusters ofstorage retrieval modules to store and exchange digital data via localarea networks within the cluster of storage retrieval modules.

BACKGROUND OF THE INVENTION

With the rising capability and flexibility of modern-day computersystems, there are increasing trends toward automation of tedious androutine functions in the handling of large volumes of data, andespecially with the volumes of data engendered in the work of financialinstitutions, for example, whereby thousands of documents such aschecks, deposit slips, remittance information forms, etc., must bechecked, sorted, corrected, totalized and returned to the banks orfinancial institutions where they originated.

Thus, many financial and banking institutions maintain large staffs ofpeople who facilitate the standard document processing procedures whichrequire that all actual items be physically handled, reviewed anddistributed to some other destination in addition to having made recordsof each of the individual transactions so that checking statements canbe made for customers and also financial data and balances recorded forthe operations of the banking or other financial institutions. Thus,much administrative overhead and handling is involved in these processeswhere various operators and administrative personnel must handle largevolumes of individual documents which must be locatable and readable,and, in the case of checks, must be imprinted upon with the standardMICR (Magnetic Ink Character Recognitional codes.

The present disclosure involves a sophisticated image and itemprocessing system which provides for greater efficiencies in thehandling of large volumes of documents and information. Thus, instead ofdealing with the actual documents for processing operations, the systemoperators and administrative personnel, in facilities of these bankingor financial institutions, can use imaging systems which store images ofthe applicable documents. The operators can view the image data on imageworkstations and thus reduce the requirements for handling paperdocuments.

Thus, by working from document images on an image workstation, theoperator is able to spend much less time and effort searching throughstacks of paper and to devote more time for the processing of documents.The use of electronic images, instead of manual handling of physicaldocuments, provides a new way of performing document processingfunctions.

A schematic overview of the general system for image and item processingis shown in FIG. 1A. The image and item processing system is composed ofa number of modules which intercooperate to provide the requiredfunctions in the processing of documents in high volume and at highspeed. These items include the high-speed document processor 8 andimaging module 8₁, the Storage and Retrieval Module (SRM) 10, the imageworkstations 12, the image printer workstations 14, the encodingdocument processor 2, and the host computer system 6.

The system uses imaging technology to capture and process images ofdocuments for item processing. Document images are stored and retrievedso that operators may perform various of the required activities whenusing the document image. These various types of activities are enabledby the application software being used.

In the operations of FIG. 1A, for example, financial institutions usethe image and item processing system to electronically capture images offinancial documents as they pass along the transport track in thedocument processor 8. After the images are captured, they are convertedto digital data. The digital data is then sent to a disk storage devicewhere it is later retrieved for display at the various imageworkstations. Operators may then perform data entry activities on thedocument image retrieved. Thus, institutions which handle large volumesof documents, such as banks and other financial institutions, may reducethe time and steps required to process a large volume of documents.

The document processor 8 is a high-speed, fast-sorting machine. It readsthe magnetic ink character recognition code line (MICR) on documents asthey flow through the transport and endorses them with the financialinstitution's endorsement. Further, it microfilms the documents as theypass the microfilmer and then uses previously programmed instructions tocomplete the customer sorting requirements by sending each document to aparticular and appropriate pocket. The high-speed document processor 8serves as an image capture site. Documents pass through the imagingmodule 8₁, FIG. 1B where images are lifted from the documents atreal-time sorter speed. The imaging module 8₁, FIG. 1B digitizes,processes, and compresses the captured images. The resulting data issent to the Storage and Retrieval Module 10 in FIG. 1A.

The host computer 6 is connected to the document processor 8 through aninterface which enables the document processor to receive the sortingparameters from the host 6 that will determine how it should sort thedocuments. The documents are read, endorsed, microfilmed, imaged, andsorted according to these parameters. After a first pass, the documentprocessor 8 sends the acquired document code line data to the host. Thehost 6 is a mainframe computer which manages the entire system andstores all master data files except the image files.

The Imaging Module 8₁ is housed in the document processor 8 and providesthe imaging capability for the system. It captures front and back imagesof documents and converts the image data to digital form. The ImagingModule 8₁ then combines the image and document data into image packetsfor transfer to the Storage and Retrieval Module 10.

The Storage and Retrieval Module (SRM) 10, which is the subject of thisapplication, stores the image packets until an image workstation 12 orprint workstation 14 requests them for display or printing. The SRMtransfers the image packet over a network to the workstations.Additionally, the SRM 10 receives modified document data from the imageworkstations (after the operators have performed data entry activities)and then sends it to the host 6.

The Image Workstation 12, of which there may be multiple numbersavailable, is the primary user interface for the system. It generallywill have a high-resolution, 15-inch, monochrome, gray-scale monitorwindow with a high-performance data entry keyboard and an optionalalpha/numeric keyboard. Thus image data is sent from the SRM and ahigh-resolution image can be made to appear on the monitor window. Theseimage workstations can be located in a typical, quiet office environmentrather than immediately in the computer room in order to provide acomfortable work place.

The main input device from operator to the workstation 12 is the dataentry keyboard which is designed to facilitate image manipulation andhigh-speed data entry. Thus, an operator can zoom, pan, flip, or rotatea document image with one simple keystroke.

The communications processor 4B (FIG. 1A) facilitates communicationbetween the host 6, the SRM 10, and the encoding document processors 2of FIG. 1A.

The encoding document processors 2 are used for certain specificapplications such as the re-entry of rejected documents and items andalso for "power encoding" which is a process which automatically encodesitems passing through a document processor with data previously enteredby operators at their image workstations 12. These document processors 2will pass document data through the communications processor 4B over tothe host 6. When doing the power encoding function, the encodingdocument processor 2 (in one embodiment) is capable of encoding 3,800documents per hour. Thus, when operators place groups of documents intothe automatic feeder on the encoding document processor 2, the documentsautomatically move into the transport track, which then takes them pastthe MICR reader and the encoder module and then out into the varioussorted packet modules. The encoder module prints the MICR or OpticalCharacter Read (OCR) characters onto the items as they flow through thetransport. The typical operation is that the documents will be encodedwith certain numerical amounts such as dollars and cents.

The print workstation 14 of FIG. 1A uses a type of image printer whichinvolves a 300-dot-per-inch, non-impact laser printer that can print onstandard 81/2-inch×1-inch paper in order to provide hard copy of imagesor data items or text.

As a result of this cooperative hardware in the image and itemprocessing system, there is enabled a setup of increased productivity,there is increased speed of operations because of the image-basedprocessing capability, and there is an increased operator efficiencysince there is no need to physically handle paper documents which can becalled up on the image workstations. Further, there is a "flexibility"possible through modular configuration and by the addition of othermodular units to increase capacity and with the provision of a quietwork environment through individual workstations such that the qualityof the operator's work life eliminates fatiguing operations and improvesoperating efficiencies.

SUMMARY OF THE INVENTION

This disclosure involves the organization of a single storage retrievalmodule used in an image and item processing system which handles highvolumes of documents at exceedingly high speeds. The singlestorage/retrieval module includes an optical interface for receivingoptical data and converting it to digitized electrical data which ismanaged by a storage processor which passes it to a disk controller unitfor storage on disk. For retrieval purposes, a second processordesignated as a "unit processor" can simultaneously operate, uponrequests from a host computer or a workstation, to retrieve selecteddata from the disks through a disk controller and transmit the data to aworkstation through a local area network controller. The storage andretrieval module also includes a communication processor whichcontinuously informs the main host computer with details of informationand activities relating to the image and item data.

The Storage and Retrieval Module (SRM) 10 of the image and itemprocessing system is a high-speed, magnetic disk controller whichperforms a number of essential functions supportive of the image anditem processing system. It retrieves and stores images from the imagingmodule. It transfers images to the Image Workstations. It transfersimages to the Print Workstations. It transfers images to andcommunicates with other SRM's which can be interconnected. Further, itsends copies of document identification data to the host computer andthen also provides image and system file management services to theother hardware components of the system.

Each SRM has a minimum of two hard-disk drives and can support as manyas eight disk drives. Additionally, the SRM can support as many as fourLocal Area Network (LAN) links, each of which can connect a maximum ofeight image workstations and print workstations for the purposes ofretrieving, manipulating, and printing stored images and data. Thus atotal of 32 image workstations and print workstations may be supportedby only one SRM.

The architectural configuration of the SRM includes multiple printedcircuit board assemblies plus two disk drives (minimum) and a MultibusII backplane. The printed circuit board assemblies include aPoint-to-Point Optical Link Controller board which receives imagepackets from the Imaging Module. The next element is the storageprocessor board which allocates space on the disk drives for storingimage packets and holds the image packets until the data amount reachesa pre-established size. A concurrently operating unit processor boardreads and buffers image packets from the disk before sending the packetson to the workstations. The unit processor is also responsible forproviding the state control for the SRM such as ONLINE/OFFLINE.

The next printed circuit board is that of the disk controller boardwhich prepares image packets for transmittal to the disk drives andhandles all disk control functions and errors. The storage and retrievalmodule can have two disk controller boards that can support as many asfour disk drives each. Another board is that of the unit processor boardwhich controls internal communications through a Multibus II backplane.

The next board assembly is the LAN controller which enablescommunications between the SRM and the host computer, the workstationsand other SRM's. Each external connection has its own LAN controller.

The two disk drives are used to provide up to 1.2 gigabytes (GB) ofstorage capacity for each disk drive while the Multibus II backplaneconnects all of the various SRM boards. This backplane also providesdata movement and interprocessor communications functions while alsosupporting arbitration, execution, I/O data movement and support for theprinted circuit board configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic drawing of the overall hardware elements involvedin the image and item processing system;

FIG. 1B is a block diagram of system modules;

FIG. 2A is a block diagram indicating the data flow between the hardwareelements involved in the image and item processing system;

FIG. 2B is a block diagram of the Storage and Retrieval Module and itsconnection to the host computer;

FIG. 3A is a diagram showing the Point-to-Point Optical Link between theImaging Module and the Storage and Retrieval Module;

FIG. 3B is a block diagram of the Point-to-Point Optical LinkController;

FIG. 4A is a block diagram of the Storage and Retrieval Module (SAM);

FIG. 4B is a diagram of one embodiment of the SRM indicating the printedcircuit boards connected within;

FIG. 5A is a block diagram of the storage processor board;

FIG. 5B is a diagram indicating data flow of document and image data;

FIG. 5C is a detailed block diagram of the storage processor;

FIG. 6 is a block diagram of the disk controller board;

FIG. 7 is a block diagram of the LAN controller board;

FIG. 8 is a block diagram of the Unit Processor board;

FIG. 9A is a diagram of the Storage/Retrieval Module Subsystemoperation;

FIG. 9B is a schematic drawing of the image packet;

FIG. 9C is a list of items usable for the image header of FIG. 9B;

FIG. 10 is a simplified block diagram of the Storage/Retrieval Module;

FIG. 11 is a drawing of related parts of the File Management Systemmodules;

FIG. 12A is a schematic of the Structured File Set Object Organization;

FIG. 12B illustrates the Index Record Structure;

FIG. 12C shows the Index File organization;

FIG. 13 is a schematic drawing of the volume structure used by theStorage Retrieval Module on disk space;

FIG. 14A illustrates a Structured File Set;

FIG. 14B shows the Index File in relation to the Logical Structured DataFile;

FIG. 14C illustrates the Logical Structured Record in relation to thephysical record;

FIG. 14D illustrates the Physical Data Record organization;

FIG. 15 is a drawing showing the system having local and remoteintercooperating Storage/Retrieval Modules;

FIG. 16 is a block diagram showing the optical link to theStorage/Retrieval Module;

FIG. 17 is a detailed block diagram of the Optical Link controller forreceiving digitized optical signals from the image module.

DESCRIPTION OF PREFERRED EMBODIMENT

The image and item processing system uses a Point-to-Point Optical Linkto connect an imaging module 8₁ to a Storage and Retrieval Module 10.Each document processor 8 (FIG. 1) has one imaging module 8₁. A singleImaging Module 8₁ interfaces to a single Storage and Retrieval Module10. This module is also called the Image Capture Module or ICM. FIG. 3Aillustrates the interconnection between the Imaging Module and theStorage Retrieval Module. The interconnection is accomplished through aPOL (Point-to-Point Optical Link) cable assembly. Thus, there are seenPoint-to-Point Optical Link (POL) controller boards which are used foreach imaging module interconnection to the SRM. One of thePoint-to-Point Optical Link controllers resides in the Imaging Module 8₁and the other Point-to-Point Optical Link controller resides in the SRM10. The Optical Link controller assemblies are linked through a fiberoptic cable, called the POL cable assembly, which consists of a duplex,fiber optic cable with Fiber Distributed Data Interface (FDDI)connectors on both ends. FIG. 3B shows a simplified block diagram of thePOL controller.

The SRM's may be enhanced by interconnecting them to each other to forma subsystem known as the Storage/Retrieval Subsystem (SRS). Each SRMinterfaces to and supports the image storage requirements of the imagesbeing captured on the Image Capture Module (ICM) 8₁ of the documentprocessor 8 where the storage is provided by use of high-performancemagnetic disk drives.

A maximum of six SRM units may be clustered together via a high-speeddata connection to provide a shared capture environment. The maximumcapacity of the SRS is generally 12 SRM's or storage retrieval units.

In addition to providing the basic image storage capability, the SRSalso supports retrieval of images from storage for transmission to theattached workstations, printers and to other SRM's.

There are additional functions which are provided by each of the SRM's10 and these include: (i) image file management (ii) workstation andprinter interface management, and (iii) system file management, and (iv)unit management.

As seen in FIG. 4B, there are a number of hardware functions provided bythe SRM. These include:

(1) a magnetic disk write and read function which is implemented via anExtended Storage Module Drive (ESMD) interface 10_(dc) ;

(2) an ESMD interface controller 10_(dc) to the disks which arecontrolled by the SRM which operates at a data transfer rate of 2.5 MBper second. A maximum of 4 gigabytes of disk (formatted) may becontrolled by each SRM;

(3) a LAN (local area network), (IEEE 802.3) controller 10_(c) functionused to connect workstation printers;

(4) a LAN (IEEE 802.3) controller 10_(c) function for communication tothe host processor 6;

(5) a LAN (IEEE 802.3) protocol controller 10_(c) to interconnect theSRM's;

(6) a system bus 10_(m) to allow the above functions to communicate toeach other within the SRM itself.

FIG. 4A shows a generalized block diagram of the components of the SRM10. All of the items are interconnected by the Multibus II 10_(m). Thevarious components include the Storage Processor 10_(p), the diskcontroller 10_(dc), the unit processor 10_(u), the Point-to-PointOptical Link Controller 10_(po), the LAN Controllers 10_(c1), 10_(c2),and 10_(c3). Attached to the disk controller 10_(dc) is a series of diskdrives 20. The LAN controllers connect respectively to the host 6, theimage workstation 12, and the auxiliary SRM's by means of LANconnections. The Point-to-Point Optical Link Controller 10_(po) connectsto the Point-to-Point Optical Link in the imaging module 8₁.

SRM Data Flow: The image data and non-image data enter the SRM togetherin the form of an "image packet". The Imaging Module 8₁ sends the imagepacket and, after the image packet enters the SRM 10 through thePoint-to-Point Optical Link assembly 10_(po), it is then sent over theMultibus 10_(m) to the Storage Processor 10_(p).

The Storage Processor board 10_(p) (FIGS. 4A, 4B) allocates disk spacefor the packet. It buffers, via buffer memory 10_(pb) the image packetsuntil there is enough data for a buffer transfer to be made to disk.Then it formats the data, prepares the disk space, and then transfersthe data to the disk controller board 10_(dc).

The disk controller board 10_(dc) receives the image packet and preparesit for transmittal to the disk drive location which was defined by theStorage Processor 10_(p). Data is then transferred from the diskcontroller board 10_(dc) to the disks 20. The image packet is stored onthe disk until the SRM module 10 receives a request to retrieve theselected image packet or group of packets. Image packets are retrievedthrough a read and transfer of the packet data. The image data which isstored on the disk is not altered or erased.

A message specifying the data to be retrieved is sent from the imageworkstation 12 to the Unit Processor assembly 10_(u). The Unit Processor10_(u) forwards the request to the Storage Processor 10_(p). The StorageProcessor 10_(p) receives the request and translates it into a commandto locate the disk space in which the particular data resides. TheStorage Processor assembly 10_(p) then sends the command back to theUnit Processor assembly 10_(u). The Unit Processor 10_(u) sends thecommand to the disk controller assembly 10_(dc) which then generates thecommand to retrieve the data from the disks. The data is retrieved fromthe disks and sent back to the Unit Processor 10_(u) by means of thedisk controller 10_(dc).

The Unit Processor 10_(u) transmits the data to a workstation LANcontroller 10_(c2) (FIG. 4A) and the assembly sends the data over theLAN to the image workstation 12 or the printing workstation 14 for whichthe request was processed.

Because the Storage Processor 10_(p) and the Unit Processor 10_(u) usethe same disk controller assembly 10_(dc), the disk accesses by theprocessor assemblies are coordinated by the storage processor commandsequencer. The Multibus II transport protocol also enables communicationbetween the different controllers in the SRM.

It is possible to organize many different configurations in the SRM,each configuration of which is built from the basic configuration. Thebasic configuration consists of the SRM cabinet, a configuration ofelectronics gates and two disk drives. The minimum electronics gateconfiguration includes the Multibus II backplane, the Storage Processor10_(p), the Unit Processor 10_(u), three LAN communication controllerassemblies 10_(c1), 10_(c2), 10_(c3), and one Point-to-Point OpticalLink Controller assembly 10_(po), plus one disk controller assembly10_(dc) that supports the two disk drives 20.

In FIG. 4B there is seen a configuration of the SRM 10 where a number ofEthernet controllers are used for communication to clusters ofworkstations. Also, additionally shown is the extended system magneticdisk controller and buffer memory section.

Multibus II Backplane: The Multibus II backplane connects all of thecontroller and processor printed circuit boards required for the SRM 10in one backplane by using a common interconnection scheme. Thisinterconnection thus provides a flexible, high-speed transfer mechanismbetween the printed circuit boards. The Multibus II supports multipleprocessor systems and multiple operating systems.

Point-to-Point Optical Link Controller Printed Circuit Board: ThePoint-to-Point Optical Link Controller circuit board is an assemblymanufactured based on fiber optic technology. Optical links are requiredin order to support the very high data rates required for efficientimaging applications. The Point-to-Point Optical Link controller boardprovides a fiber optic communication interface, in addition to bufferingthe data being sent, and also handles all Point-to-Point Optical LinkController communication errors. It provides central services modularfunctions required for the Multibus II parallel system bus, whichservices deal with system initialization, system clock generation, andsystem failure.

The SRM 10 communicates directly to the Imaging Module 8₁ and indirectlyto the Document Processor 8 by means of a point-to-point optical linkconnection to Imaging Module 8₁. This connection is terminated at eachend by a point-to-point optical link controller board seen in FIG. 3A,and which is under the control of the SRM Unit Processor board 10_(u).The Point-to-Point Optical Link Controller assembly uses an Intel 80286microprocessor for its central processing unit (CPU). This board handlesduplex serial communication over a pair of serial fiber optic links.

Storage Processor Printed Circuit Board: Image packets of data are sentfrom the Imaging Module 8₁ to the SRM 10 over the Point-to-Point OpticalLink shown in FIG. 3A. The Point-to-Point Optical Link Controller, shownin more detail in FIG. 3B, receives the data, processes it, andtransmits the data to the Storage Processor 10_(p) of FIG. 4A. TheStorage Processor 10_(p) stores or buffers the image packets receivedfrom the Imaging Module 8₁ by storing it in buffer memory, 10_(pb), FIG.4B.

When the image data is fully buffered, the Storage Processor 10_(p)board controls the writing of image data to disk storage and thebuilding of files on the hard disks. The Unit Processor 10_(u) readsimage packets from the disks. It then buffers (via 10_(ub) FIG. 4B) theimage packets before sending them to the image or printing workstations12 and 14 (FIG. 1A).

The central processor used within the Storage Processor 10_(p) is theIntel 80386, Microprocessor which is a 132-pin device that fetchesinstructions and data from various resources such as the memory, the I/Ocontroller and other modules connected to the printed circuit boardinterface.

Disk Controller Board and Disk Drives: The Disk Controller 10_(dc) (FIG.4A) is a Multibus II single-board computer that can handle as many asfour disk drives such as 20, of FIG. 4A. The disk controller 10_(p)buffers data and handles all disk control functions and errors. The diskcontroller 10_(dc) board is made up of a processor, a memory system, andinterface circuit groups.

The Disk Controller Board is based on the Intel 80186 Microprocessorwhich controls the disk drive hardware and manages the storage andretrieval of image packets to and from the magnetic disks. Since theStorage Processor 10_(p) and the Unit Processor 10_(u) both concurrentlyaccess the disk controller board 10_(dc), the disk controller 10_(dc)coordinates disk accesses that read and write image packets to the diskdrives. The 80186 Microprocessor provides the computing and I/Oresources to control the disk drives.

The disk drives 20 of FIG. 4A provide high-capacity and high-performancestorage for the image and item processing system. The SRM 10 providesdisk space for "system" files, "structured" files and "sequential" filessystem services software which are described later herein. These storageservices are provided to applications running on the host computer 6,the image (12) and printing (14) workstations, and the Imaging Module8₁.

The disk drives use a high-speed extension of the Storage Module Device(SMD) interface standards, and this interface is referred to as ESMD.

One disk controller 10_(dc) can support from one to four disk drives andeach disk drive is made up of two control boards, a sealed disk unit,and the power supply.

Each SRM 10 uses a minimum of two hard disk drives and can support asmany as eight drives. The SRM cabinet can be expanded by adding anadditional module in order to support more than four drives.

LAN Controller Printed Circuit Boards: A set of LAN controller boardsprovides communication between the SRM 10 and the host computer 6, plusadditional storage and retrieval modules, and the image workstations 12or printing workstations 14. The LAN Controllers (10_(c1), 10_(c2),10_(c3)), provide the physical interface to handle communication overthe host-LAN Controller 10_(c1), over the SRM-LAN Controller 10_(c3) andthe workstation-LAN Controllers 10_(c2).

The LAN Controller printed circuit boards are Intel iSBC 186/530 printedcircuit board assemblies. The iSBC 186/530 printed circuit boardassembly is designed to operate in and to support message-based,multiprocessor system architectures working in conjunction with theMultibus II parallel system bus.

The host-LAN Controller 10_(c1) with its connection to thecommunications processor 4B (FIG. 1A) allows the storage and retrievalmodule 10 to communicate with the host computer 6. The Unit Processorboard 10_(u) controls the communication activities to the host computerLAN.

The SRM-LAN Controller 10_(c3) allows the SRM to communicate with otherSRM's such that these communications are controlled by the UnitProcessor board 10.sub..

The LAN Controller 10_(c2) (FIG. 4A) enables the SRM 10 to communicatewith the Image 12 and Printing 14 workstations. The Unit Processor10_(u) also controls communications to the LAN's of workstations.

Unit Processor Printed Circuit Board: The Unit Processor 10_(u) controlscommunication by means of the LAN Controllers 10_(c). The Unit Processorperforms buffering, state management, communications management anderror handling functions. It uses specialized system software toinitialize the hardware and the interconnects, to handle tests and errormessages, to allocate resources to applications programs, and toschedule various tasks to be accomplished. The Unit Processor 10_(u) isan Intel 386/116 single-board computer and is located on the bus 10_(m)of FIG. 4B.

Software Operations: The software is installed at the host computer 6,and all code and date files are released on tape for loading into thehost 6. The software downloads information to the SRM 10 from the host6. Copies of the SRM 10 software operating systems reside on each SRMhard disk, enabling the SRM to boot the operating systems in the eventof disk failure. Booting from the hard disks permits the SRM moduleswithin the system to be initialized concurrently.

The SRM module 10 provides for the initialization of the Imaging Modules8₁, Image Workstations 12 and Printing Workstations 14 which areconnected to it. It supports downloading of software from the hostcomputer 6 for updates to itself, the Imaging Module 8₁, and the ImageWorkstations 12 and Printing Workstations 14. Each SRM 10 has formatteddisk drives and the system software for the SRM module 10, the ImagingModule 8₁, and the Image Workstations 12 and Printing Workstations 14.The software operating within the SRM 10 resides in an Intel 80386Microprocessor system environment. This includes Programmable Read-OnlyMemory (PROM) based firmware, which boots the full system software fromthe hard disk during booting.

The basic operating system in the SRM 10 is that of Intel's iRMXII whichis a multi-tasking operating system that provides basic file managementservices such as the creation and maintenance of directories, filemapping and file integrity verification.

Software Architecture: The SRM module 10 uses a software set whichconsists of the Intel iRMX operating system and system servicessoftware. The iRMX operating system is loaded from the hard disksfollowing the completion of the built-in self-test (BIST). There arefour sets of system services which operate in the iRMX environment whichinclude (i) the communication services; (ii) the file managementservices; (iii) unit management, and (iv) diagnostic services.

The SRM 10 stores and operates communication services and file-relatedservice classes, the service classes being groups of related systemservice commands. The communication services reside in all the systemmodules of the image and item processing system in order to provide acommon communication service set within the system. The "file-related"services reside only in the SRM 10.

Communication Services: These represent a basic and unified mechanismfor message-based interprogram and intertask communication. Theseservices are used to communicate among the various modules of the imageand item processing system. These services can be used directly or as abase upon which more specialized mechanisms can be constructed. Thecommunications services are installed in all of the modules of the imageand item processing system.

File-Related Services: The SRM 10 runs a specialized set of file-relatedsystem services in order to manage the files stored in the hard diskdrives. There are four classes of such file services:

(a) file system,

(b) common file,

(c) sequential and system file,

(d) structured file.

The file system services are used to manipulate and manage file systems.In this class, a file system is an information storage container wherethe contents and organization of the file are relevant. File systemservices are concerned with: (i) creating and deleting storage files,(ii) retrieving statistics and file attributes, (iii) allocatingphysical storage resources to files, (iv) storage subsystem managementand administration.

The common file services are used to open and close files, rename anddelete files, and modify file attributes. These services exercise thefollowing capabilities:

(b1) a file association between the operator and a file;

(b2) deleting a file from a file system;

(b3) modifying attributes that are unique to each file, such asauthorization;

(b4) changing the name of a file.

The sequential file services will access the contents of a stream orsystem file. Stream files contain codes and information required forprinting. Sequential/system files consist of a sequence of bytes,typically no larger than 1 MB in length. Data transfer operationsspecify only the number of bytes to be transferred from the currentposition in the file.

The structured file services will access the contents of the system'sstructured file. A structured file is an information storage objectconsisting of a sequence of records. Each record is composed of anidentical collection of fields. Individual fields may be of a fixed or avarying length and may include program-supplied data of arbitrary value,image files, or they may be empty.

Unit Management Services: These provide a means to manage the SRM byhandling state control, statistics, error notification and errorrecovery.

Functional States: The SRM 10 communicates four functional states toother modules within the image and item processing system. These are:

(f1) the initializing state;

(f2) the off-line state;

(f3) the reserved state; and

(f4) the on-line state.

The on-line state (f4) is the normal operational state of the SRM 10. Itsupports the complete communication and file management capabilities ofthe Storage and Retrieval Module. The off-line (f2) is that conditionwhere the SRM 10 is capable of handline most of the externalcommunication services requests, but it does not do file servicesrequired in the on-line state. In the reserved state (f3), the SRM 10can support diagnostic-related functions where the SRM 10 can belogically disconnected from the other modules in the system for testpurposes.

In the initializing state (f1), a sequence begins at power-on where allof the printed circuit boards in the SRM 10 will run built-inself-tests. Then extended built-in self-tests on these printed circuitboards are done after which the Point-to-Point Optical Link Controller10_(po), the Storage Processor 10_(p), and the Unit Processor 10_(u) areused to boot the full operating system from disk. The sequence iscompleted by the Unit Processor 10_(u) which completes the sequence byloading the LAN operating system from disk into the LAN Controllerboards 10_(c).

Point-to-Point Optical Link Controller Board: As seen in , FIG. 3A, thePoint-to-Point Optical Link Controller 10_(po) provides the interfaceconnections between the Imaging Module 8₁ and the Point-to-Point OpticalLink Controller 10_(in) the SRM 10. As seen in FIG. 3A, there is onePoint-to-Point Optical Link Controller in the Imaging Module 8₁ whichconnects to another duplicate Optical Link Controller 10_(po) in the SRM10. The Optical Link Controller handles communication over the POL,Point-to-Point Optical Link. It provides a fiber-optic communicationinterface, provides for buffering of data being transmitted and handlesall communication errors between the optical link controllers.

Using an Intel 80286 Microprocessor, the Optical Link Controller handlesduplex serial communication over a pair of serial fiber optic links at arate of 20 MB per second.

FIG. 3B shows a block diagram of the Optical Link Controller whichincludes a control processor 30, an optical transmitter interface 40, anoptical receiver interface 50, interconnect space circuitry 44, and theparallel system bus interface circuit 46 which connects to the parallelsystem bus 10_(m).

The Optical Link Control processor 30 of FIG. 3B manages all theprotocol associated with transmitting and receiving data over the fiberoptic link. The Intel 80286 Microprocessor has EPROM and dynamic RAM forstorage of data and code. This control processor 30 also includes I/Ocircuitry, interrupt controllers, programmable timers, and serialcommunication controllers for system software and diagnostic support. Inthe preferred embodiment, the Optical Link Controller 10_(po) provides 2MB of dynamic RAM memory and 128K bytes of EPROM (Erasable ProgrammableRead Only Memory).

The interface circuit 46 of FIG. 3B is called the iPSB interface and isused to provide the logic needed to interface to the iPSB bus 10_(m).The parallel system bus (PSB) interface allows communication between theOptical Link Controller board and other controllers in the SRM 10. Theinterface circuit 46 is made up of three basic components: (46a) amessage-passing coprocessor; (46b) an interconnect circuit; and (46c)the iPSB buffers.

The message-passing coprocessor 46a controls all of the references tothe iPSB interface 46, the interconnect circuit space operations in 44,and the message-passing protocol for the memory and I/O circuitry. Themessage-passing coprocessor provides a data path between the local busand the iPSB interface 46. It also supports the Multibus II messagepassing on the bus 10_(m). Message passing on the PSB bus 10_(m)provides the direct transfer of data and command messages from oneprinted circuit board to another printed circuit board in a high-speedburst mode. Also, local bus communication is accelerated by themessage-passing coprocessor. Additionally, the message-passingcoprocessor provides for error detection and reporting, local bushandshake control and external address buffer control.

The interconnect circuit-portion (item 46_(b) above), is shown in FIG.3B as the interconnect space circuitry 44. This is a separate addressspace on the Multibus II, 10_(m), that allows for dynamic configurationof I/O in memory, remote diagnostic testing and reporting, and printedcircuit board identification.

The iPSB dual-port buffers (of items 46_(c) above) operate such thataddress information from the buffers and control information from themessage-passing coprocessor are passed directly to the parallel systembus 10_(m).

Multibus II System Services: As seen in FIG. 4B, the Multibus II,10_(m), is connected to all of the printed circuit board assemblies ofthe SRM 10. There is a control position in the middle of the Multibus10_(m) which is called "Slot 0". The printed circuit board assembly thatresides in this Slot 0 is designed to hold a module called the CentralServices Modules, and this position is used to identify each printedcircuit board assembly on the Multibus 10_(m). Each printed circuitboard assembly carries a unique signal indicating its assembly type andlocation.

The Point-to-Point Optical Link Controller 10_(po) provides the centralsource for general purpose central bus functions which include systemclock generation, system initialization, bus time-out detection andpower fail handling, but this controller only provides these functionsif it is located in Slot 0 of the parallel system bus backplane (locatedat 10_(m) of FIG. 4B).

Optical Receiver Interface: The Optical Receiver Interface 50 of FIG.3B, receives serial data from the Imaging Module 8₁ over the fiber opticlink. The fiber optic receiver accepts the incoming optical signals andconverts these into electrical signals which are then processed by aclock recovery circuit to generate a clock signal for the image data.The data is checked for framing to detect the start and stop ofmessages. All synchronization is removed from the signal to leave onlythe transmitted data.

Within the Optical Receiver Interface board 50 (FIG. 3B) there iscontrol logic which decodes the received data and converts it to aparallel data stream. This data is stored in a FIFO (first-in first-out)buffer for later unloading by a direct memory access controller therein.Additionally, the Optical Receiver Interface 50 performs cyclicredundancy checks for messages to detect errors in transmission. Thedirect memory access controller has four channels and is configured toallow the reception of image data such that the Optical ReceiverInterface 50 permits the reception of image packet data andcontrol/status information.

Optical Transmitter Interface: The Optical Transmitter Interface 40(FIG. 3B) of the Optical Link Controller 10_(po) transmits serial datafrom the Imaging Module 8₁ over the fiber optic link where a fiber optictransmitter converts electrical signals to optical signals. The OpticalTransmitter 40 receives parallel data from storage, serializes the data,encodes the data using Manchester encoding, and then transmits theserial data over the fiber optic link 9_(po). Internal control logichandles the encoding and transmission of data, which logic alsogenerates a cyclical redundancy check to ensure that the transmitterdata can be verified at the receipt point. Additionally, the logicframes the data being transmitted.

In the image item processing system of this disclosure, transmission ofimage data is accomplished with "packets". A packet is a block of datafor transmission. Each packet holds compressed image data for one to 35documents and has "header" information to correlate the image data tocertain document information stored in the host computer 6. The imagepackets are buffered to allow for short-term variations in thetransmission rate. The "image header" is part of the image packetcontaining information to correlate the image data to documentinformation stored in the host computer 6 and to allow later retrievalof images. In this context the "image" is the digital representation ofone side of a document, such as one side of a check or one side of aremittance slip.

Storage Processor Board and Processor Circuit: After receiving the imagepackets from the Imaging Module 8₁, the Storage Processor board 10_(p)executes file management functions by organizing and ordering the imagepackets into files. These functions are performed by the processorcircuit 60 of FIG. 5A.

The processor circuit 60 provides central management to the activitiesof the Storage Processor 10_(p) and to the entire SRM operation. Theprocessor circuit 60 controls image and document data sent to theStorage Processor 10_(p) from the Image Module 8₁.

FIG. 5B shows the disk management role of the Storage Processor circuit60, where it organizes and orders the data into files and transfersthese files for writing on the disk drives (20). The disk controller10_(dc) (FIG. 4A) recalls the files upon request of the StorageProcessor 10_(p).

The processor circuit 60 of 10_(p) (FIG. 5A) controls the writing ofimage packets to disk storage and the subsequent building of files ondisks by buffering the data, forming it into files and preparing it forstorage on disk as seen at item A on FIG. 5B. The processor circuit 60then manages the transfer of data to the disk controller 10_(dc) as seenby the channel B in FIG. 5B. The disk controller board 10_(dc) thentransfers the files to the extended storage module disk drive 20 forstorage as seen in channel C of FIG. 5B.

The processor circuit 60 consists of the Intel 80386 processor CPU andan advanced direct memory access controller (ADMA) and direct memoryaccess (DMA) data buffers.

The Intel 80386 Microprocessor 60 (FIG. 5C) operates to fetchinstruction data from various of the resources such as memory, I/O andboards connected to the parallel system bus interface 10_(m). Themicroprocessor has 4 gigabytes of address space in a 32-bit data path.The microprocessor also allows space for up to 256 different interruptvectors.

The ADMA (61, FIG. 5C) provides for the direct memory access capabilityof the Storage Processor board 10_(p). It provides for independentdirect memory access channels and can transfer data at rates up to 10.7MB on an 8 MHz clock. It is capable of performing 32-bit, single-cycledata transfers to and from the parallel system bus interface to supportmessage passing. The storage processor board also has two channels ofadvanced direct memory access configured to handle the message-passingcoprocessor, 68_(p) of FIG. 5C.

The ADMA controller 61, FIG. 5C, supports both synchronized andunsynchronized direct memory access operations with command and datachaining. The ADMA connects up to 16 MB of memory or I/O spaceregardless of which operating mode the 80386 Microprocessor is in.Direct memory access works by transferring data directly between memoryand the I/O devices without involving the Microprocessor which resultsin higher speeds for data transfer operation.

The address buffers 64, FIG. 5C, are used to buffer addresses for use bythe ADMA controller and the 80386 Microprocessor which both share thelocal bus.

FIG. 5C illustrates the basic components of the storage processor 10_(p)in greater detail than that of FIG. 5A.

Referring to FIG. 5C, the processor circuit 60 is made up of a processorcentral processing unit (CPU) 60_(p), the advanced direct memory accesscontroller 61, and the DMA address buffers 61_(b).

The memory circuit 66 has a tag memory 66_(t), a cache memory 66_(c), anerasable PROM 66_(m) and a Dynamic RAM 66_(a).

The I/O circuit 70 is provided with a set of timers 70_(t), an interruptcontrol circuit 70₁, and an IBX circuit 70_(x).

The iPSB (parallel system bus) 10_(m) provides connection to a messagepassing coprocessor 68_(p), dual port buffers 68_(b), and a serial I/Omicrocontroller 68_(c).

The Dynamic RAM 66_(d) of the memory circuit 66 is connected to a set ofdata buffers 66_(b) and an address circuit 66_(x).

The address buffers 64 are connected to the memory units 66_(t), 66_(c),66_(m), and the address circuit 66_(x). Additionally, the addressbuffers are connected to the CPU 60_(p) and to the timers circuitry70_(t).

The data buffers 62 are connected to the CPU 60_(p) and also to thecache memory 66_(c), the dual port buffers 68_(b) and the data buffers66_(b).

The memory circuit 66 of the Storage Processor board 10_(p) buffersincoming image packets received from the Imaging Module 8₁ in its memorycircuit group. A memory circuit group 66 includes the tag 66_(t), thecache 66_(c), the Erasable PROM 66_(m), and the Dynamic RAM 66_(d).

The tag memory 66_(t) optimizes the cache memory operations. Once theCPU 60_(p) requests data, the data that is received is tagged with anaddress and stored in the cache memory 66_(c). After this all datarequests are passed by the tag memory to see if the data is available inthe cache memory 66_(c).

Data requested by the CPU 60_(p) is kept in the cache memory 66_(c).When a specific piece of data is requested, the tag fields are read andif the address field matches, the request goes directly to thehigh-speed cache memory instead of the slower Dynamic RAM memory 66_(d),thus speeding data access.

The cache memory 66_(c) allows zero weight-state read accesses to memorywhen the data requested is resident in the cache memory. The 64K byteStatic RAM cache memory 66_(t) has 16K, 4-byte entries. Each entryconsists of a 32-bit data field. Each 32-bit word in the Dynamic RAM(DRAM) 66_(d) array maps to exactly one entry in the cache memory66_(c). A tag field is used to determine which four bits of DRAM 66_(d)currently reside in a cache entry. The combination of a direct-mappedcache array and tag fields insures data integrity and accurateidentification of cache "hits". On a write cycle, data is written toboth the cache memory and the DRAM memory array. Cache "misses"(involving memory reads not found in the cache) cause the data field ofthe cache entry corresponding to the addressed memory to be filled fromthe DRAM array 66_(d).

In FIG. 5C, there are two 32-bit EPROM sites, 66_(m) which allow 256Kbits of erasable memory which are supplied for the Storage Processor10_(p). These sites are reserved for EPROM and are used for the built-inself-test diagnostics (BIST) and the boot loader resident on the boardassembly.

The DRAM 66_(d) uses a daughterboard assembly to provide additional DRAMmemory. This Storage Processor daughterboard provides an additional 12MB of memory. DRAM provides byte parity for error detection since parityis used to check to see if data has been transmitted correctly. Anon-maskable interrupt to the CPU microprocessor 60_(p) is generatedupon detection of a parity error. Although the DRAM memory 66_(d) isphysically located on another board assembly, it is accessed by theStorage Processor assembly 10_(p) as if it were located on the mainStorage Processor board 10_(p). The DRAM 66_(d) is dual-ported to allowaccess from either the on-board processor 60_(p) and the advanced directmemory access controller 61, or by other board assemblies connected tothe iPSB interface circuit 68.

As seen in FIG. 5C, the I/O circuit group 70 includes timers andinterrupt controllers used for general functions. A programmableinterval timer (PIT) 70_(t) includes three independent, programmable,16-bit interval timers/counters. The input to all three timers is a 1.25MHz clock signal. Outputs from these timers are routed to the inputs ofthe interrupt control 70₁. Access to the PIT by the Microprocessor CPU60_(p) requires seven wait states.

The interrupt control circuit 70₁ involves Programmable InterruptControllers (PIC's) which are used in a master-slave configuration forprocessing on-board interrupts. These two programmable interruptcontroller devices 70₁ provide 15 independent levels of interruptpriority.

The iSBX interface circuit 68 of FIG. 5C provides one 16-bit connectorfor further I/O expansion. The iSBX interface circuit 68 operates withseven wait states for the Microprocessor 60_(p). This interface is notused in normal operation, but is used during system debug.

The iPSB interface circuit 68 uses a message-passing coprocessor 68_(p)which supports the Multibus II message passing. Message passing on theiPSB bus 10_(m) provides direct transfer of data and command messagesfrom one board to another board in a high-speed burst rate. The messagepassing coprocessor 68_(p) accelerates local bus communication andallows the transfer of messages at a speed independent of the speed ofindividual processors or controllers. The message-passing coprocessor68_(p) provides a 32-bit data path between the local bus and the iPSBinterface circuit 68. The coprocessor 68_(p) also functions to provideinterface arbitration and transfer control, error detection andreporting, local bus handshake control, external address control andinterconnect operations (interconnect space).

On the Multibus II, 10_(m), there is provided an "interconnect space"which is a separate address space that allows dynamic configuration ofthe I/O circuitry and memory, remote diagnostic testing and reportingand printed circuit board identification. This interconnect space iscontrolled by an I/O microcontroller 68_(c). Most of theseconfigurations options are communicated to the microcontroller 68_(c)through interconnect space over the message-passing coprocessor 68_(p).The microcontroller 68_(c) also performs initialization of the StorageProcessor board, 10_(p).

In the iPSB interface circuit 68, there is a set of dual-port buffers68_(b) so that the iPSB interface can handle dual-port accesses to theon-board DRAM address space. This interface provides start and endingaddress decoding as well as all iPSB protocol control.

Disk Controller Board and Disk Drive: After the Storage Processor board10_(p) formats the image packet data and prepares the disk space, ittransfers the data to the disk controller board 10_(dc) (FIG. 4A).

In FIG. 4A, the disk controller 10_(dc) connects to a cluster of diskdrivers 20 on one end and connects to the Multibus II, 10_(m), on theother end. After the Storage Processor 10_(p) formats the image packetdata and prepares the disk space, it transfers the data to the diskcontroller 10_(dc). The disk controller receives the image packet andprepares it for transmittal to the storage processor-defined disk drivelocation. Data is then transferred from the disk controller 10_(dc) tothe disks 20. The image packet is stored on the disk until the SRM 10receives a request to retrieve the selected image packet or group ofpackets. Image packets are then retrieved through a read and transfer ofthe packet data. The image data stored on disks cannot be altered and itremains in disk storage until the application program requests itsdeletion.

The image workstation 12 sends the Unit Processor 10_(u) (FIG. 4A) amessage that indicates the specific data to be retrieved. This requestis transmitted to the workstation LAN controller board 10_(c1) in theSRM 10. The message is passed on to the Unit Processor board 10_(u)which forwards the request to the Storage Processor board 10_(p).Storage Processor 10_(p) receives the request and translates it into acommand to locate the disk space in which the data resides. The StorageProcessor 10_(u) then sends the command back to the Unit Processor10_(u). Because the Storage Processor 10_(p) and the Unit Processor10_(u) use the same disk controller board 10_(dc), then disk accesses bythe processor boards are coordinated by the Storage Processor 10_(p).

Disk Controller Board: The Disk Controller 10_(dc) is a Multibus II,single-board computer that controls the disk drive hardware. It managesthe storage and retrieval of data travelling to and from magnetic diskstorage. The Disk Controller operates to buffer data, to coordinate diskcontrol functions, and to handle disk errors. The Disk Controller10_(dc) is made up of a processor, a memory, a disk interface, andparallel system bus interface circuit groups.

The disk controller processor circuit in the controller 10_(dc)functions to control the disk drives, to manage disk requests from thesystem, to manage caching functions and to control the interconnectspace. The disk controller processor controls the disk drive hardwareand manages the storage and retrieval of data to and from magneticstorage. Since the Storage Processor 10_(p) and the Unit Processor10_(u) access the disk controller board 10_(dc) concurrently, theprocessor circuit of the disk controller coordinates disk accesses thatread and write image packet data to the disk. The Disk Controllerprocessor also manages the caching functions, plus disk requests fromthe system, by using algorithms that optimize controller operations.

The disk controller processor in the Disk Controller 10_(dc) is based onthe Intel 80186 Microprocessor. This processor provides the computingand I/O resources to control the disk drives, plus the other functionsof cache management, handling disk requests and executing the algorithmsinvolved. The 80186 is a 16-bit processor with two independent channelsof direct memory access, a programmable interrupt controller, three16-bit timers, a programmable memory and peripheral chip-select logic ofwhich the interconnections and circuitry blocks are shown in FIG. 6.

The two DMA direct memory access channels in the Intel 80186 processorare used to support message transfer between the local memory and themessage-passing coprocessor of FIG. 6. Direct memory access operates totransfer data directly between the memory in FIG. 6 and the I/O deviceswithout requiring interaction with the CPU of the processor 60_(p) ofFIG. 5C. The central processor is bypassed in the data transfer allowinghigh-speed data transfer operations.

In order to read from or to write to a memory chip, it is necessary tosignal the device that is being addressed. This is done by the chipselect logic which formulates the chip select signal which selects onememory chip among the various chips available. It is necessary to supplythe address of the selected data within the memory. Chip select logicselects the controller chip and also selects the I/O on the diskcontroller board 10_(dc).

Memory Circuity of Disk Controller 10dc: The memory circuit in FIG. 6provides DRAM, EPROM and cache memory. The DRAM is used for datahandling and buffering; the EPROM is used for firmware storage and thecache memory is used to speed memory access. There are 64K bytes ofonboard DRAM for the 80186 Microprocessor code and data storage. TheEPROM memory has 64K bytes used to store firmware for the diskcontroller board 10_(dc). The cache memory in FIG. 6 provides a bufferstorage of 512K bytes. This allows multiple tracks of data to be placedin controller-resident memory. The caching enables data to be accessedin the memory much more rapidly.

Disk Interface Circuit: This provides a disk controller chip and buffersfor the interface. It handles all the control status and data signalsfrom the disk drive and provides the DMA channel to move data betweenthe disk and the cache memory.

The Disk Controller 10_(dc) has a parallel system bus interface circuitshown in FIG. 6 which provides communication between the disk controllerboard 10_(dc) and other controllers in the SRM module 10. The diskcontroller board interfaces to the parallel system bus 10_(m) through amessage-passing coprocessor, interconnect space and buffers.

The message-passing coprocessor of FIG. 6 controls all references to theiPSB interface circuit, interconnect space operations andmessage-passing protocol for the memory and I/O circuits. Themessage-passing coprocessor of FIG. 6 supports the Multibus II 10_(m)message passing. Message passing on parallel systems bus 10_(m) providesthe direct transfer of data and command messages from one board toanother board in a high-speed burst rate. The message-passingcoprocessor also enables disk data to be burst across the bus whileconsuming a minimal amount of bandwidth. Commands, status information,and data are exchanged between the controller and the host 6 using themessage-passing coprocessor. The parallel system bus interface circuithas dual-port buffers. This enables the iPSB interface of FIG. 6 tohandle dual-port accesses to the onboard DRAM address space providingstart and end address decoding as well as protocol control.

Disk Drives: The disk drives 20 of FIG. 4A provide high-capacity,high-performance storage for the image and item processing system. Diskspace is provided for operating system software, for system servicessoftware, for image workstation applications software, and image datapackets, as will be shown in connection with FIG. 13. The disks may alsobe used for application software that runs on image workstations,printing workstations 14 and Imaging Module 8₁.

The drives use a high-speed extension of the SMD (Storage Module Device)interface standards and this interface is referred to as ESMD. The ESMDhard disk drives are 8-inch, magnetic drives containing 14 platters.Each disk drive provides an unformatted capacity of 1,000.2 MB. Eachdisk drive is made up of two printed circuit boards, the sealed diskdrive unit and power supplies. As seen in FIG. 6, signals are passedfrom the disk controller 10_(dc) board to the main control board by wayof the A and B cables. The disk controller board 10_(dc) connects to thedisk drive itself by means of A and B cables. The A cables interfacecarries disk control signals. The B cables interfaces carry data signalsto and from disk drives. Disk cable A is an internal interconnectionfrom the disk controller 10_(dc) to as many as four disk drives. The Acable carries control signals while the B cables are point-to-pointconnections from the printed circuit board assembly to the drives. Thecable A is daisy-chained between each of the four disk drive connectors.

The disk drives are mounted in drive modules within the Storage andRetrieval Module 10. The drive modules are in self-contained drawerswherein each drawer houses two disk drive assemblies and their powersupplies. A control circuit board in the disk drives functions toprovide interface control, drive status control, read/write control,head positioning servo control and disk rotational speed control.

Local Area Network Controller Board: FIG. 7 shows a block diagram of theLAN controller 10_(c). This board assembly involves Multibus II,single-board computers that handle communications over local areanetworks. The SRM 10 uses the LAN controller 10_(c) to control andprovide physical communication interfaces for the three separatecontroller shown in FIG. 4A which are the host-LAN controller 10_(c1),the image workstation-LAN controller 10_(c2) and the SRM module-LANcontroller 10_(c3).

One host-LAN controller 10_(c1) is required in each SRM 10. A minimum ofone and a maximum of four workstation-LAN controller boards, such as10_(c2), can be installed in the SRM 10. Each one can communicate withone to eight image and printing workstations. The SRM-LAN controllerboard 10_(c3) is used in systems which require transfer of data betweenmultiple SRM modules. Thus the SRM 10 contains a unique LAN controllerfor each local area network in the image and item processing system. TheLAN control boards in the SR 10 will have counterparts in the hostcomputer 6, the workstations 12 and other storage and retrieval modulesinterconnected in the system.

The SRM 10 communicates with the host computer 6 using the host LANcontroller board 10_(c1) which is connected to the unit processor10_(u). The Unit Processor board 10_(u) controls the host-LANcommunication activities. The workstation LAN controller board 10_(c2)enables the SRM 10 to communicate with the image 12 and printing 14workstations. Again, the Unit Processor 10_(u) board controls theworkstation LAN communication.

As seen in FIG. 7 which shows a block diagram of the LAN controllerboards 10_(c). the main processor circuit initiates and controls thecontroller board operations. It includes an 80186 Microprocessor andsupport latches and transceivers, so that the controller can support theLAN functions required in message-based multiprocessor systems. Theprocessor is a 16-bit, 8 MHz Intel 80186 Microprocessor with two directmemory access channels, three interval timers, a clock generator and aprogrammable interrupt controller.

In the LAN Controller of FIG. 7, the Microprocessor direct memory accesschannels support message transfer between local memory and themessage-passing coprocessor, and the direct memory access channels arecontrolled by direct memory access requests sent by the message-passingcoprocessor. The 80186 Microprocessor has two multiplexed address anddata lines which are sent to sets of buffer and transceiver chips in thecontroller processor circuit. The demultiplexed output of these buffersand transceivers become the local memory bus. This connection to the busis the link between the control processor circuit and other elements ofthe LAN controller board.

The LAN controller board 10_(c) has one LAN communication channel. Thedevice on the other end of the LAN cable is a LAN transceiver which usesthe IEEE 802.3 interface which is implemented by a LAN coprocessor and aIEEE 802.3 serial interface device.

The IEEE 802.3 serial interface component performs Manchester encodingand decoding of the transmit and receive frames. It also provides theelectrical interface to the IEEE 802.3 transceiver cable. Either theIntel 82501 Ethernet serial interface chip or the SEEQ 8023A Manchestercode converter chip may be used to serve as the interface device. Theserial interface also provides collision detection, receive clockrecover, and data modulation functions. The LAN coprocessor manages alltransactions over the LAN interface. The coprocessor is a highlyintegrated device which provides the framing, the link management, andnetwork management functions required for Ethernet communications.

The LAN controller 10_(c) of FIG. 7 has a memory circuit consisting of alarge DRAM array and a set of ROM/EPROM memory facilities. The DRAM inthe memory circuit of FIG. 7 has 512K bytes of memory capability. TheRAM memory contains code and data. The EPROM involves devices from 8Kbytes to 64K bytes per device and acts to receive address informationdirectly from the local address bus and provide data to the local memorybus. The EPROM memory contains code and data.

The interconnect circuit block of FIG. 7 is basically an I/O subsystemwhich provides timers, interrupt controller, and an RS232C serial portfor debugging and testing. The PSB interface in FIG. 7 is the parallelsystem bus interface circuit which gives the LAN controller 10_(c) thecapability for access to other boards on the bus 10_(m). The PSBinterface circuit includes its main component which is a message-passingcoprocessor chip. The message-passing coprocessing chip provides forfull message, memory, I/O, and interconnect access to the parallelsystem bus 10_(m). The iPSB interface circuit of FIG. 7 provides logicneeded to interface to the bus and includes the message-passingcoprocessor, interconnect circuitry and iPSB buffers.

The message-passing coprocessor controls all accesses to the iPSBinterface circuit, and controls interconnect, space operations, andmessage-passing protocol for the memory and I/O circuits. It provides adata path between the local bus and iPSB interface circuit. Thecoprocessor supports Multibus II message passing. This message passingprovides the direct transfer of data and command messages from oneprinted board assembly to another in high-speed burst mode. The iPSBinterface of FIG. 7 which also handles dual-port accesses to the onboardDRAM address space in the memory circuit. It provides start and endaddress decoding as well as iPSB protocol control.

Unit Processor Board: As seen in FIG. 4A, the Unit Processor board10_(u) is connected to the Multibus II, 10_(m). Now, with reference toFIG. 8, there is shown a block diagram of the Unit Processor 10_(u). TheUnit Processor handles internal SRM module communication by coordinatingthe message passing and image retrieval within the SRM. When, forexample, the image workstation 12 requests retrieval of image packets,the message-specifying-data-to-be-retrieved travels to the UnitProcessor 10_(u). The Unit Processor then forwards the request to theStorage Processor board 10_(p). The Storage Processor Board translatesthe request into a command to locate the disk space in which the dataresides. The retrieval of data continues when the Storage Processor10_(p) returns the command to the Unit Processor 10_(u). The UnitProcessor 10_(u) sends the retrieval commands to the disk controllerboard 10_(dc) which then accesses the disk and retrieves the data. Thedata is retrieved from the disk and then sent back to the Unit Processor10_(u) via the disk controller 10_(dc).

The Unit Processor 10_(u) transmits the data to the workstation LANcontroller 10_(c) and the workstation controller sends the image packetover the workstation LAN to the image workstation 12 or the printingworkstation 14 for which the request was processed.

As seen in FIG. 8, the Unit Processor 10_(u) is a Multibus II,single-board computer that performs data buffering, communicationmanagement, state control and error handling for the SRM communications.As seen in FIG. 8, the Unit Processor board 10_(u) includes theprocessor circuit, the memory circuit, the I/O circuit and the parallelsystem bus interface circuit in addition to address buffers and databuffers.

Functionally, the processor circuit of FIG. 8 provides central controlfor management of SRM communications, it monitors the activities of theLAN controllers on the parallel system bus 10_(m), and it receivescommunication messages from the LAN controllers. The processor circuitmonitors communications and passes them on to the appropriate boardsover the bus 10_(m) in addition to managing the processor sendingmessages and data out of the SRM. The processor circuit uses an Intel80386 processor (CPU), an advanced direct memory controller, and directmemory access data buffers. The 80386 Microprocessor (Intel) fetchesinstruction data from the various resources such as memory, I/O, andother boards on the bus interface. It operates with a 32 MHz clock thatis divided by two in order to achieve the 16 MHz system clock rate. TheMicroprocessor provides 4 gigabytes of address space in a 32-bit datapath.

The Advanced Direct Memory Access controller in the processor circuit ofFIG. 8 provides the direct memory access capability of the UnitProcessor 10_(u). It has four independent, direct memory access channelsand can transfer data at rates up to 10.7 MB per second on an 8-MHzclock. It can perform 32-bit, single-cycle data transfers to and fromthe iPSB interface to support message passing. The ADMA controllersupports both synchronized and unsynchronized direct memory accessoperations with command and data chaining, and these features areprogrammable by use of the internal ADMA registers. The ADMA device canaccess up to 16 MB of memory or I/O space regardless of which operatingmode the 80386 Microprocessor is in. The direct memory access works bytransferring data directly between memory and I/O devices withoutinvolving the Microprocessor and thus allowing higher speed fordata-transfer operations.

In FIG. 8, the memory circuit is used to buffer communication andtransfer of image data from the disk drive. Images are retrieved andheld in the buffer until a full image packet is accumulated. The imagepacket is then transferred out over the workstation- LAN 10_(c) or theSRM-LAN controller 10_(c3). Included in the memory circuit group are atag memory, a cache memory, EPROM memory and DRAM memory.

The tag memory optimizes the cache memory operations. Once the 80386Microprocessor requests data, it is tagged with an address and stored incache memory. Following this, all data requests are passed by the tagmemory to see if the data is available in the cache memory. Datarequested by the 80386 Microprocessor is kept in the cache memory andthe next time that a specific piece of data is requested, the tag fieldsare read and the request goes directly to the cache memory instead ofthe larger memory. The 64K byte SRAM cache memory has capacity of 16K,with 4-byte entries. Each entry consists of a 32-bit data field and each32-bit word in the DRAM array maps to exactly one entry in the cachememory. A tag field is used to determine which four bytes of DRAMcurrently reside in a cache entry. The combination of a direct-mappedcache array and tag field ensures data integrity and accurateidentification of cache "hits". On a write cycle, data is written toboth the cache and to the DRAM array. When cache "misses" occur, thiscauses the data field of the cache entry (corresponding to the addressmemory) to be filled from the DRAM array.

The DRAM memory in the memory circuit of the Unit Processor 10_(u) usesa daughterboard to provide additional room for DRAM. The daughterboardprovides an additional 4 MB of memory. The DRAM is dual-ported in orderto allow access from either the onboard processor and the AdvancedDirect Memory Access or by other boards on the parallel bus interface.The data buffers shown in FIG. 8 accept data and hold it until it isreleased to the disk controller board 10_(dc). The Unit Processor board10_(u) can buffer image packets up to one-half cylinder or 40K bytes insize.

The I/O circuit of FIG. 8 conveys data to the Disk Controller 10_(dc).This circuit also supports the operating system by scheduling theoperation of software processes such as memory management and interruptprocedures. Included in the I/O circuit of FIG. 8 are timers andinterrupt controllers needed to coordinate message-passing anddata-transfer activities.

In FIG. 8, the parallel system bus interface circuit provides the logicneeded to interface to the parallel system bus 10_(m). The interfacesubsystem is made up of a message-passing coprocessor, an interconnectspace circuit, a dual-port controller and a set of buffers. Themessage-passing coprocessor in the interface circuit of FIG. 8 alsosupports the Multibus II address spaces by initiating message passing.Message passing on the bus 10_(m) provides the direct transfer of dataand command messages from one board assembly to another. Themessage-passing coprocessor provides a 32-bit data path between thelocal bus and the iPSB interface. It also provides for interfacearbitration, transfer control, error detection reporting, local bushandshake control, external address buffer control and interconnectoperations.

Referring to FIG. 10, there is seen a schematic drawing of the Storageand Retrieval Module system with all its PC boards interconnected to theMultibus II system 10_(m). There are basically two operating CPU's whichcan operate "concurrently" to provide storage and retrieval services.

The Storage Processor 10_(p) operates in order to provide for thestorage of data on the disk drives 20. When the flow of captured imagedata from the image module 8₁ provides a bit stream of 2 MB per second,this is received by the point-to-point optical link controller, 10_(po)and is conveyed for handling to the Storage Processor 10_(p) whichprocesses it for conveyance to the disk controller 10_(dc) where it canthen be stored on the disk drive 20.

Simultaneous and concurrent retrieval operations for transmitting imagesto the workstations can be effectuated by use of the second processorCPU 10_(u), called the Unit Processor 10_(u). The Unit Processor 10_(u)communicates via the Multibus II with the Disk Controller 10_(dc) inorder to retrieve data from the disk drive 20 where data can then beconveyed to the Ethernet and LAN controllers 10_(c) which can conveythem to the requesting workstations.

From the viewpoint of the entire financial image system, the SRM 10 is abuffer between the image capture module (ICM, 8₁) and the workstations12 which are used to view the images generated by the ICM.

The SRM 10 will accept document packets from the ICM 8₁ and cantemporarily save them in its buffer memory or on its disk drive 20 andsubsequently can send these document packets on to workstations 12. FIG.10 illustrates the simplified version of the SRM 10 and how the flow ofimage data can occur from the ICM 8₁ to storage on the disk drives andalso for retrieval from the disk drives to the workstations 12.

The data, which may reach 2 MB per second, arrives from the ICM 8₁ intothe point-to-point optical link controller as a document packet. Thedocument data is moved from the point-to-point optical link controllerto the buffer in the Storage Processor 10_(p) of FIG. 10. Then whenenough data is accumulated to fill a disk cylinder, the data is moved tothe disk controller 10_(dc) and written onto a disk 20.

The basic unit of storage in the SRM 10 is a "Record", as viewed fromthe application services. For the image processing applications, theusage is such that a "block" of Records (up to 3,000 Records) may begrouped into a file for subsequent balancing purposes. The SRM 10 canfile approximately 2.5 images per disk track, which is approximately 65images per cylinder. Buffer memory is provided to buffer a completecylinder amount of data, and then execute a full cylinder "write" todisk. Normally, an entire block of image data would take up more diskspace than one cylinder. Image data on disk is accessed by reading the"header information" (in its standard format, wherein the headercontains all the detailed information about the particular image such asits length, its pixel data, its compression condition and any algorithmsused with it. The header information will then permit the system to findthe relevant addresses for separating the image data field from theentire Record.

It might be indicated that each check document has a "code file"reference which is encoded in magnetic ink at the bottom area of eachcheck. Additionally, when documents are placed in a sorter such asdocument sorter 8, they are given a block number identification andadditionally are given a sequence number according to their sequentialposition in that block of documents. The information regarding the codefile, the block identification, the sequence number and also themonetary amount of a given check or document, are all types ofinformation which are passed between the host computer 6 and the imageworkstations 12 by means of application programs and are not passed tothe storage/retrieval module 10 from the document sorter 8 via thepoint-to-point optical link 9_(po).

When some number of images are required by a workstation 12, theappropriate data is read from a disk 20 into the disk controller 10_(dc)and moved to the buffer on a second CPU designated the Unit Processor10_(u). Then at the appropriate time, the image and any associated datais moved from the second CPU of the Unit Processor to an Ethernetcontroller 10_(c) for transmission to the requesting workstation 12.

In order to manage and control all the disk activity, the first CPU (theStorage Processor 10_(p)) uses the disk storage controller 10_(dc), andthis manages all of the disk Read/Write operations. The second CPU (UnitProcessor 10_(u)) uses the Lan-workstation controller 10_(c) and thismanages all the data transfers to and from the workstations, 12.

In order for the first CPU (Storage Processor 10_(p)) to perform its owndisk data transfer operations, there is used a File Management System(FMS) which resides on the Storage Processor Board 10_(p). Additionally,the FMS has a Remote Module (RM) executing on the second CPU (UnitProcessor 10_(u)). When a system or application module requires a diskoperation, it calls one of the interface routines in the Remote Module(RM) of the FMS. This RM communicates with the main FMS module on thefirst CPU board (Storage Processor 10_(p)) and then performs its owndisk transfer. Using this operation, it is possible not to overburdenthe bandwidth of the first CPU (Storage Processor 10_(p)) by requiringall disk data to pass through it. The control commands used in the FMShave an insignificant effect on the overall transfer rate since thenumber of commands for each image is very small compared to the numberof 32-byte data messages required to transfer a 20K byte image.

File Management System (FMS): The FMS includes a complete set ofprocedures through which all the application programs can create, read,write, and otherwise manipulate disk files. The FMS is the interfacethrough which all application programs access the disk storage moduleswhich are connected to the Storage/Retrieval Module (SRM) 10. The FMS isconstructed above the Intel standard RMX Nucleus and Basic I/O System(BIOS). The RMX Nucleus and modules involve the software and firmwareused for Intel processors and are available as a commercial item.Whenever possible, the functionality of the RMX modules are used todirectly implement functions in the FMS.

As seen in FIG. 11, the FMS is organized to have a Sequential FileManager (QFM) and a Structured File Manager (SFM), and, as seen in FIG.11, contains the following major modules:

(a) Sequential File Manager (QFM);

(b) Structured File Manager (SFM);

(c) Image File I/O System (IFIOS)

(d) Basic I/O System (BIOS);

(e) Device Driver (DD).

File Systems: The disk storage space connected in an SRM 10 ispartitioned into a certain number of areas, each of which area is calleda "File System". Each File System encompasses one or more disk drives.Each file maintained by the FMS is contained within exactly one FileSystem.

Each File System is denoted by a File System Name and can contain anarbitrary number of Sequential Files and an arbitrary number ofStructured File Sets. Each of the Structured File Sets can contain thestandard RMX Data Files, Image Data Files, and Index Files.

The storage and retrieval module SRM 10 may be considered as a multi-bustube design. The dual processor architecture basically provides a datamanagement system for handling image data packets.

The software operating system is a system designated RMX by Intel Corp.of Santa Clara, Calif. It involves the Intel network architecturesoftware which does networking at a base level and which is used todrive the modules in the Storage/Retrieval Module 10. This softwareinitializes itself in an efficient manner and can talk to the hostcomputer 6. It also provides services to the other storage and retrievalmodules so that it is possible to provide image data management.

As was previously discussed in connection with FIG. 10, the RMX softwareprovides the features of allowing reads and writes simultaneously plussimultaneous storage, and high-speed image storage of images from thesorter plus high-speed retrieval of these images making use of the twoprocessors, that is the Storage Processor 10_(po) and the Unit Processor10_(u).

The image data comes from the Image Module 8₁ of the document sorter 8and winds up on the high-speed disks in order to provide a data base.The RMX software controls all of the retrieval of images from the disks.Coordination is effectuated by the use of the Point-to-Point OpticalLink Controller 10_(po) which can talk to the Image Module 8₁ andprovide control signals between the SRM 10 and the Image Module 8₁. Thepoint-to-point optical link controller can be considered as a high-speedmulti-bus tube having a fiber optic base which provides a multi-busoptical tube connection between the image capture module 8₁ of thedocument sorter 8 and the storage and retrieval module 10. The datatransmission over this point-to-point optical link is on the order of21/2 megabytes per second.

The parallel processing arrangement between the two CPU's, that is theStorage Processor 10_(p) and the Unit Processor 10_(u), provides aparallel processing function where one CPU is dedicated to handling thestorage of image and item data while the other CPU is dedicated tohandling the retrieval. The Multibus II, 10_(m), allows paralleltransmission and can support up to 30 megabytes of data per second, thuspermitting the first and second CPU to operate in a simultaneous fashionfor both storage and retrieval.

The file system functionality is highly organized toward image datamanagement. Thus the type of documents used in this system, such aschecks, will have images of the front side and also the back side. Thefile system lends itself to any application software writer so that whena file is created, they can identify images so that it is possible tosee the fronts of the checks, if desired, and also to see the backs ofthe checks, if desired. Additionally, it lends itself to seeing bothfronts and backs with the MICR data, or without it, so there isconsiderable flexibility in structuring. The file system constitutes aplatform which supports a wide window of applications.

One efficacious feature of the financial imaging system used with thestorage and retrieval module is that the system is highly distributed.Various functions are handled and provided through individual modulessuch that not many applications need to interrupt the mainframe, thusspeeding the operations of the system.

The file management system has the unique feature in that it logicallyorganizes images and documents via high level service applications thatallow for optimal processing where speed is a major factor. Thus, aspreviously mentioned, there are separate files for the front of checksand separate files for the back of checks and separate files for theMICR information, and so on. This allows operators to access all of thisinformation, or only such selected information as is required at anygiven time.

Thus this system provides means for application programs to store andsubsequently retrieve images. The stored images are organized in termsof named, ordered aggregations, or sequences, of images. Also,individual stored images are identifiable by specification of the nameof the sequence within which an image is resident, or by system-suppliedidentifiers, record numbers and/or application-supplied "key values".Thus, to any sequence of stored images, an application program would beable to: create and designate the name of the sequence; designate orascertain the locale within the system where the sequence is to bestored; copy images from one sequence to another; determine thenumber-identities and storage size of images stored within a sequence;append images to the end of a sequence, specify identifying key values;retrieve images from a sequence in order of storage (randomly or in keyorder); delete sequences no longer needed; obtain exclusive access to asequence.

The storage and retrieval subsystem can include one or moreStorage/Retrieval Modules 10. The SRM collects the compressed image datafrom the imaging module 8₁ and temporarily stores it on high speedmagnetic disks 20. Once the data is stored, then the image work stationoperators and printer work stations can retrieve this data from the SRM10. In general, the SRM performs the following functions:

(a) receives and stores images from an imaging module 8₁ ;

(b) transfers images to image work stations 12;

(c) transfers images to print work stations 14;

(d) transfers images to and communicates with other SRM modules;

(e) sends copies of document identification data to the host 6;

(f) provides image and system file management services to other modulesin this system.

Each SRM 10 provides from 2.4 to 9.6 gigabytes of storage capacity. Inoperation, any image work station operator can retrieve image data fromany one of the storage/retrieval modules in the system. Each SRM iscapable of storing as many as 60 images per second (or 30 front imagesand 30 back images) and retrieving them at a rate of 22 images persecond. This is considered more than adequate to keep up with requestsof operators working at the image work stations 12.

As seen in FIG. 9A, a variety of system software modules are providedwithin the Storage/Retrieval Module 10. These have been designated withvarious block numbers for differentiation. The Initialization Services150 causes the hardware and software environment to be configured in themanner that permits the storage and retrieval module operating system tobe loaded from disks and started. A Disk Initialization Service providesthe capability to selectively initialize portions of the SRM disks 20. ASystem Loader resides in EPROM within the SRM 10 and provides functionsto load the SRM-operating system code files from the SRM disk or via aIEEE 802.3 communications link. In FIG. 9A, the SRM CommunicationsHandler 105 supports the processing of a restricted set of systemservice messages. It transmits only those messages that support theinitialization or diagnosis of the SRM 10. It also controls thesegmentation of system messages so that outbound messages are dividedinto segment packets that are consistent with requirements of theInterface Driver. Inbound message packets received from the InterfaceDriver are assembled or concatenated into messages. The SRMCommunications handler 105 finally processes all SRM messagescommunicated to or from the host 6. The host IEEE 802.3 driver (item131) provides the device level control of the communications link. Thehost Initialization Service 132 establishes the communications linkbetween the storage/retrieval module 10 and the host 6.

The following software functions are included in the Storage/Retrievalmodule on disk-based operating system. Once the SRM operating systemcommences, it initializes the local environment to support the executionof multiple processes. The SRM Communications Handler 105 (FIG. 9A)performs the routing of system service requests and responses within theStorage/Retrieval Module 10. The Image Command Services 106, in FIG. 9A,provides access to disk storage and retrieval functions. These functionsare supported by the System Disk Handlers and the ESMD Driver. AnException Services module 152 performs all status and statistics datacollection and recording functions. This data is retained in both RAMmemory and on disk and is periodically transmitted to other units withinthe overall system. Transfer of this data occurs after receipt ofsystems service requests which are initiated by other units.

Communications with other Storage/Retrieval Modules in the system arehandled by the SRM-SRM Services module 140. This module supportscommunications to the other storage and retrieval modules within thissame cluster by means of the IEEE 802.3 local area network. The ImageCommand Services 106 handles all disk-related processes, including imageand standard system file management and local disk directory management.The Workstation Services 116 modules handle communications to and fromthe Storage and Retrieval Module to both the image workstations 12 andthe image printers 14. These functions include providing direct controlover Ethernet lines IEEE 802.3) to which the workstations are connected,plus initial processing of systems service requests from theworkstations and the routing of messages to workstation destinations.

The image capture module software of ICM services 104 consists of an ICMMessage Server 103_(b), an Image Data Packet Queuing Manager 103_(a),and point-to-point optical link driver 102, which provide thefunctionality for the Storage/Retrieval Module 10 to communicate withthe image capture module 8₁. A Local Logs module keeps track of the logsdefined by the system and is responsible for collection and reporting ofthe data requested by the applications and the system.

The point-to-point optical link (POL) controller synchronous interface,10_(po), as seen in FIGS. 4A and 4B operates at a data rate of 20megabits per second and is used to communicate to the associated imagecapture module ICM 8₁. Additionally, the POL is also used forcommunication between various clusters of Storage/Retrieval Modules 10.An IEEE 802.3 local area network controller 10_(c3), FIG. 4A, (LAN)supports communications to the other SRMs within a cluster. A similarlocal area network supports communications with the workstations 12, anda separate local area network controller supports communications withthe host 6.

A more detailed discussion and examples of usage regarding FIG. 9A ispresented hereinafter, after a discussion of the various filingstructures used in storage of and retrieval of data packets.

The Storage/Retrieval Module 10 involves files and file systemsincluding certain types of file structures and classes of systemsservices that manipulate the files and the file systems. The classesinvolved are: (i) file system services; (ii) common file services; (iii)sequential file services; (iv) structured file services.

The "File Systems services" are used to manipulate and manage filesystems. A file is an information storage container used such that thecontents and organization of the file are not particularly relevant. The"File System services" are concerned with problems such as creating anddeleting storage systems, systems retrieval of statistics and fileattributes, allocation of physical storage resources to files, andstorage system management and administration.

The Common File services are used to open and close files, to rename anddelete files and to modify file attributes.

The "Sequential" and "Structured File" services involve two differentmethods of accessing the contents of files such that each presents adifferent view of how the contents of a file are organized.

The actual physical storage resources are divided into "file systems".Each file system uniquely controls the storage space allocated to it andstorage space is not shared among file systems.

A "file system" is composed of one or more "volumes" (FIG. 13). A volumeis a quantity of storage space that is available for allocation toindividual files and "file systems" may contain from one to eightvolumes.

A file system is a "named object" in the system directory and a "filename" identifies a particular file within a file system, but it is notan object in the system directory. The file systems possess propertieswhich are maintained in the System Directory. The System Directoryservices retrieve and maintain file system entries in the SystemDirectory.

File Types: There are two basic types of files in this systemenvironment and these are (i) sequential files and (ii) structuredfiles.

(i) A "sequential file" is an information storage object consisting of asequence of bytes but typically no larger than one megabyte in length.Data transfer operations specify only the number of bytes to betransferred to or from the current position in the file. The currentposition is marked by a zero-based file pointer. The file pointer ispositioned within the file by performing seek operations.

(ii) A "structured file" is an information storage object consisting ofa sequence of records. Each record is composed of an identicalcollection of fields. Individual fields may be of a fixed or varyinglength. They may include images or program-supplied data of arbitraryvalue or they may be empty.

A "record" must have one key field. The key field houses a supplementaldata structure called an "index".

The "index" is used to identify a particular record within a structuredfile. Indexes are maintained by this system in an index file. The "indexfile" is set up by the file management system when the structured fileis created. The system software maintains an index file based oninformation supplied by the application through File System andStructured File services.

From an applications viewpoint, a structured file appears in terms ofrecord, field, and index structures. This logical view is mapped, underapplication control, into one or more physical data files. The physicaldata file, defined by File System services, provides the actual storageresources for a structured file, and is accessed by the system inresponse to retrieval requests. Each physical data file is defined so asto house one or more structured file fields. Record fields may bereplicated among multiple physical data files in order to enhanceperformance or to improve availability during retrieval operations.

Structured File services are used in conjunction with an "association"established between an application program and a structured file. Theassociation is established when a structured file is opened. It isterminated when the structured file is closed. The association providesa framework for managing services performed on a structured file. It isalso a repository for information such as the next occurrence of arecord to be "read from" or "written to". Each association existsbetween exactly one program and exactly one structured file and isindependent of all other associations.

Data retrieval of a structured file is performed in a defined retrievalsequence or it can be done randomly. A retrieval sequence is a subset ofthe records within a structured file. It may be either a range of keyvalues or an orderly sequence of random key values. After a retrievalsequence has been specified for an association, services can be invokedto retrieve the individual records and the fields that make up thesequence.

To retrieve an image, the storage/retrieval module needs the followinginformation: (a) the file system name; (b) the file name; (c) theretrieval index (RIX); (d) the appropriate authorization.

The file system name is the name of the file system that the particularfile is located in. This is a disk organization parameter configuredinto the system. The file name is the name of the file the image orimages are stored into. This is the "structured file" type. There can bemany files defined or created within a file system. The retrieval index(RIX) is the identifier of the specific record within a file, and isused for retrieval purposes. This is sometimes referred to as the record"key". The financial information system (FIS) "system directory", whichresides in the host 6, is configured with several authorizations, someof which define and specify which users or programs can access images.This information is loaded into a storage/retrieval module forverification when needed. Generally, the information required forretrieval would follow sequences such as: FILE SYSTEM; FILE NAME; RIX;PROGRAM NAME.

The application program will provide images to a workstation operator sothat the operator may check balances and prove out various informationand sums. There are various layers of software interfaces which providethe functions to actually get an image for a workstation.

File System Services: These services manage and maintain the resourcesof file systems and include such services as: create file system, deletefile system, get attributes file system, get statistics file system,search file system, set attributes file system, synchronize file system.

An "attribute" is a characteristic about a file system that can beselectively retrieved and modified. File system attributes provideinformation about the operational state of a file system.

File system attributes include such characteristics as: changeauthorization, delete authorization, image space available, spaceavailable, space in use, and other useful types of attributes.

Common File Services: The common file services provide a group of toolsthat manipulate both sequential files and structured files. Theseservices provide the capability for creating a "file association"between the user and a file, and for modifying attributes that areunique to each file, and deleting a file from a file system, and forchanging the name of a file. These types of common file servicesincludes: close file, delete file, open file, rename file, setattributes file, verify file integrity.

The file attributes make information about the files selectivelyavailable within a file system. Commonly used file attributes are suchitems as: access time, file type, last record, owner's name, spaceallocated, space available, and a number of other types of attributes.

Sequential File Services: These sequential file services manipulate andprovide access to sequential files to provide for such items as: createsequential file, get statistics sequential file, read sequential file,seek sequential file, write sequential file.

Structured File Services: The structured file services manipulate andprovide access to the structured files. These services include: copystructured file records, create structured file, delete from structuredfile, find structured file, get statistics structured file, read nextstructured file, select structured file, write structured file, and anumber of other useful services.

The present system uses the structured file services which provide theflexibility often associated with data base management systems. Asalient feature is the ability to maintain a relatively abstract andsimple-to-use view of data, despite a complex mapping onto physicalstorage resources.

Structured file services do not incur the same level of complexityassociated with fully developed data management systems. The structuredfiles are "write-once" if they contain variable-length records. Theserecords are appended to a structured file, but once written, a recordcannot be updated. The intent is to provide an information storagefacility both reasonably simple and yet adaptable to meet varyingapplication and physical storage environment needs.

In a logical view of a structured file, it may be considered aninformation storage "object" that consists of a sequence of records.Each record is composed of an identical collection of fields. Individualfields may be of a fixed or varying length and may containprogrammatically supplied information of arbitrary value, or they maycontain an image or they may be empty.

In those fields containing program-supplied data, one "key" field isrequired. Each key, which consists of all the data within a field, givesrise to a supplemental structure called an "index". The existence of anindex for a key allows searches for records with particular key valuesto be performed in an optimized fashion. Indexes are automaticallymaintained by the system in an index file. The index file is created bythe file management system when the structured file is created.

In regard to applications using structured files, a structured fileappears in terms of records, fields, and indexes. This logical view ismapped, under application control, onto one or more physical data files.The physical data files, which are defined by file services, are used toprovide the actual storage resources for a structured file. Eachphysical data file is defined to contain one or more of the structuredfile fields.

Fields may be replicated as needed among multiple physical data filesfor the purpose of enhancing performance or of improving availabilityduring storage and retrieval operations.

The programmer's view of a structured field is in terms of thestructured file's record, field, and index structure. Physical datafiles are accessed automatically by the system in response to retrievalrequests.

Many of the services supplied for structured files are intended to beused in conjunction with an "association" established between a programand a structured file. An association is established when a structuredfile is opened and is normally terminated when the structured file isclosed. The association provides a framework for managing servicesperformed on a structured file and is a repository for such informationas the next record to be retrieved or written to. It can be noted thatan association exists between exactly one program and exactly onestructured file and is independent of all other associations.Restrictions are not imposed on how many associations an application canmaintain with a single structured file. Multiple associations could beused to achieve the effect of multiple paths found in data base systems.

Retrievals from structured files are performed in terms of "retrievalsequences". A retrieval sequence is a subset of the records within astructured file and might be either a range of key values within anindex file or a sequence of random key values. After a retrievalsequence has been specified for an association, services can be invokedto retrieve the individual records/fields that make up the sequence.

The characteristics of all the file systems on a Storage RetrievalModule 10 are described by the contents of a constructed File SystemRoute Directory, which directory contains files for (a) system names,(b) unit names, (c) attributes.

The System Names file is the means by which external File System namesare translated to the actual RMX File System Directory path name. TheUnit Attributes file allows the system to reconfigure the drivesconnected to an SRM 10 without affecting any application programs.

File System Directory: Each File System is described by a File SystemDirectory which contains the following data files and directory files:(a) Unit Attributes which contains information as to the cylinder sizeand bytes per cylinder plus the number of cylinders per disk drive, (b)attributes, (c) sequential directory, (d) structured directory, (e)standard directory, (f) index directory, (g) image directory.

Sequential Directory: All of the sequential files in a File System arecontained in the Sequential Subdirectory of the File System Directoryassociated with the file system. The Sequential Directory contains thefollowing data files: (a) File Names, (b) a sequence number connectingone RMX file for each Sequential File named in File Names, (c)attributes.

The File Names file is the means by which the external File Names aretranslated to actual RMX File Names.

Structured Directory: The Configuration Files for each of the StructuredFile Sets in a File System are contained in a structured subdirectory ofthe File System Directory associated with the File System. TheStructured Directory contains the following data files: (a) File Names,(b) Structured File Set attribute and there is one such RMX file foreach configuration/attribute file which is named in the File Names file.

The File Names file is the means by which external Structured File SetConfiguration File names are translated to the actual RMX file names.

Standard Directory: All of the standard RMX Data Files in the StructuredFile Sets in a File System are contained in the standard subdirectory ofthe file system directory associated with the File System. The StandardDirectory contains the following data files: (a) File Names, (b) data onone such RMX file for each standard file named in File Names.

The File Names file is a means by which external standard file names aretranslated to actual RMX File Names.

Index Directory: All of the Index Files in the Structured File Sets in aFile System are contained in the index subdirectory of the File SystemDirectory associated with the File System. The Index Directory containsthe following data files: (a) File Names which contain, for each indexfile, a line showing the logical index file name related to the RMX filename, (b) an index number such that it is one such RMX file for eachIndex File named in the File Names.

The File Names file is the means by which external index file names aretranslated into the actual RMX file names.

Image Directory: All of the Image Files in the Structured File Sets in aFile System are described by files in the Image Subdirectory of the FileSystem Directory associated with that File System. The Image Filesthemselves are allocated from the image space (FIG. 13) associated withthe File System. The Image Directory contains the following data files:(a) Space Label which specifies the number of cylinders used for imagecylinders in this File System, (b) Space Files which contain informationon number of space files and a number of image space files plus thespace file name and image space file name, (c) Space Map which containsone bit for every cylinder in the image space and is used to manage theimage space allocation, (d) File Names which contains a line for eachimage file giving the logical image file name related to the RMX filename, (e) Node which indicates one type of RMX file for each Image Filenamed in the File Names. Each Node is used to determine the location ofthe image data of the associated image file and contains informationregarding the size and bytes, the total number of cylinders involved,the block count, and other information.

The Image Space associated with the File System is the total space inthe Image Space Files named in the Space Files file.

Each Image File in the File System is associated with exactly one RMXNode file which contains the location of the data in the associatedImage File. Additionally, the access rights of the Node file are used asthe access rights of the associated Image File. Logically, each ImageFile can be considered to be its associated Node file, with regard tocreating, reading and writing.

The File Names file is the means by which the external Image File namesare translated to actual RMX File names.

Structured File Manager: The Structured File Manager (SFM) operates on"objects" called Structured File Sets (FIG. 12A). A Structured File Setis a Composite Object which contains an arbitrary number of Image Files,an arbitrary number of standard RMX files, and an Index File to accessthe data in the SFS.

The chief purpose of introducing the Structured File Set mechanism is toallow an application to manipulate data as elements of logical recordsand of logical structured files, independent of how and where the datais physically stored. By divorcing the logical view of the data from itsphysical representation, the system gains the ability to modify theconfiguration of its system operation without modifying the applicationprograms.

Each Structured File Set consists of a number of files. Each of thesefiles contains Structured Records, each of which has a unique RecordNumber which can have a value of 1 to n, where n is the number ofrecords in the Structured File Set. Each Structured Record contains oneor more fields, which contain the actual data operated on by theapplication. From an application point of view, a Structured File Set isone structured file, containing "n" (logical) structured records, eachof which contains a set of fields of data. The fact that all of thefields do not reside in the same physical file, and in fact might noteven reside on the same drive, is immaterial to the application. Theactual configuration of the Structured File Set (SFS) is determined whenthe SFS is created and is based on its expected type of usage. Onereason for using the FS concept is that "Image Data" is collected on adocument-by-document basis, but is normally retrieved on animage-by-image basis. Since records in a Structured File have variablesizes, the Structured Record organization permits greater ease ofrecovery from error situations.

Index File Structures: An Index File contains Index Records which is astructure providing information as to the record index, size, the numberof fields, the record index number, the field directory entry for aseries of fields from a first field through the nth field. Then eachindex record structure can be organized into a graph of index structureswhich start from a low value and continue on to a high value for the nthindex number. This allows data records to be located by means of a keyvalue which is normally a part of the data record itself.

Sometimes it is required to locate data records, not by a Key value, butby the "number" of the records in the file. In this case there are twopossible conditions which exist:--(i) the records in the file are all ofthe same fixed length, or (ii) the records have variable lengthsunrelated to each other. If each of the records in a data file have afixed length, k, then the location of the beginning of the record n ismerely n*k bytes from the beginning of the file.

If all of the records in a data file are of variable length, a specialkind of Index File is used to locate an arbitrary record by its recordnumber. This type of Index File is given the term "Record Index File"and it contains index records with no Key value. In this case the record"n" is located in the Data File by first locating the nth Index Recordin the record index file and then using the contents of this indexrecord to locate the data record.

Record File Services: A Structured File Set (FIG. 12A) will normallyconsist of one or more Data Files and one or more Index Files.Additionally, the Structured Records in a Data File normally consist ofone or more Fields. In the narrow case where the Structured File Setcontains exactly one Data File, and each record in the Data Filecontains exactly one Field, it is possible to operate on the StructuredFile Set as if it were a Record File. This makes it possible to supportmultiple data files and fields.

When the Record File (FIG. 12B) is created, it can be done with either afixed record size (with no associated index file) or with a variablerecord sizes, with an associated Record Index File (RIX), FIG. 12C.

FIG. 12A is a schematic drawing showing the organization of the datastructures which describe a Structured File Set Object.

FIG. 12B shows the structure of one record in the Index File.

FIG. 12C shows the organization of the records in an Index File. Sincethe RIX values (RIX is the record retrieval index) are organized inascending sequence, then for a 5,000 record Structured File Set, at mostonly 12 comparisons will be required to probe the index to indicate thecorrect index record.

Configuration File Format: When a Structured File Set is created oropen, the Structured File Set (SFS) must be given information regardingall of the files which comprise the Structured File Set, and thecharacteristic of those files. This information is contained in a TextFile called the Structured File Set Configuration File. The accessrights to the entire Structured File Set (SFS) are identical to theaccess rights of the Configuration File. The Structured File SetConfiguration File contains information of the following nature:

(a) name of the structured file set;

(b) field with the field name and the data file name;

(c) the data file name and the data file type;

(d) the index file name and the field name.

With reference to FIG. 13, there is shown a schematic drawing of the"volume structure" of the storage and retrieval module, SRM 10. It maybe noted that for each individual SRM, a file system will contain anintegral number of volumes from one to eight. Each volume has a capacityof 1.2 gigabytes unformatted and there are 745 cylinders per volume and27 tracks per cylinder providing for 49,728 bytes per track. There arefour volumes allocated to each disk controller 10_(dc) and eachStorage/Retrieval Module 10 may have one or two controllers to serviceit. In FIG. 13 it may be noted that volume #1 is allocated to the filesystem A and provides a number of storage spaces as indicated by thefile names thereon. The File System B can be seen to involve twodifferent volume structures, i.e., volume #2 and volume #3 whereby theimage files are placed on two different volume structures. The FileSystem C is handled by the Volume #4 memory space as indicated in FIG.13.

Image File I/O System: The Image File I/O System (IFIOS) is provided toefficiently store data and retrieve data in image files. When the SRMdisk system is initialized, one or more large RMX files arepre-allocated on each volume. These files are called Image Space Files(FIG. 13) and the total space occupied by them is denoted as Image FileSpace. Since the Image Space Files are pre-allocated (and never getde-allocated during system operation), they are completely disassociatedfrom any basic I/O system (BIOS) operations. From the viewpoint of theBIOS, it is as if the space contained in these files did not exist sincethey will never be used for any standard file storage. This permits thesystem to be partitioned where each volume is partitioned into twological units: one unit comprising all of the space that the BIOS canallocate and modify, and one unit comprising the space in the ImageSpace Files.

Traditionally, the partitioning of a volume into multiple units is doneby defining a disk address threshold. However, in the SRM partitioningscheme, this is done by logical equivalency. No additional data isrequired to be given to the BIOS (Basic I/O System) to make it aware ofthe "other unit" on a device since its own file allocation structuresdefine the extent of the "other unit".

The space contained within the set of Image Space Files is denoted asthe Image Space Unit on the volume. A feature about this allocationmechanism is that the size of the Image Space Unit on a volume canreadily be changed, merely by re-allocating a new set of Image SpaceFiles during system initialization.

All Image Files (I Files) are allocated from the Image Space Unit on avolume. The IFIOS (Image File I/O System) file allocation structures aresimilar to the BIOS structures, except that the volume granularity isone track (36 kilobytes) and the file granularity is one cylinder (550kilobytes). This means that data is transferred to and from the disk intrack-size blocks and the I Files are allocated as an integral number ofcylinders.

This type of organization allows for good balance between the size ofthe I File records, the size of the disk buffers required for readingthe I File records, the transfer characteristics during the transfer ofmultiple I File records, and the size of an entire IFILE. It may benoted that since the IFILE granularity is one cylinder, then completecylinders can be written to and read from, with maximum efficiency.

The allocation of space in the Image Space Unit does not affect theallocation of the Image Space Files on the volume. The Image Space Unitis, logically, a contiguous area which always exists. Space for theIFILES is allocated from it and the IFILE space is returned to it uponde-allocation. Logically, an Image Space Unit can be considered as adistinct storage volume. All of the Image Space Units on the disk drivesconnected to one SRM 10 are logically concatenated to form the SRM ImageSpace. This allows the IFILES to span disk drives.

Sequential File Manager: Within the File Management System, a SequentialFile is a disk file which has no intrinsic internal structure. It isviewed by the system as merely a sequence of bytes. The Sequential FileManager (SQFM) allows primitive files to be created, to be written to,to read from, and/or otherwise manipulated.

All Sequential Files in the File System are contained in the SequentialDirectory of the File System and are always standard RMX files and neverImage Files. The name of a file can be any sequence of non-blankalphanumeric characters, which is automatically translated to an RMXfile name.

Device Driver: The Device Driver for the disk system has been enhancedwith the following features:

(a) The Device Driver transfers data to/from contiguous data buffers inthe host memory of host 6. The driver is enhanced to allow a host bufferto be a data-chain block, as permitted in the RMX systems;

(b) The Device Driver allows for a new image space device and datastructures;

(c) and the driver allows concurrent access from both the BIOS and theIFIOS.

Buffer Management: One uniquely distinguishing characteristic of thestorage and retrieval module, SRM 10, as compared with other real timesystems, is the large amount of data which must be manipulated. Thus,optimization of the data movement is the salient characteristic of theSRM. Since resources are finite, there is a fixed amount of buffermemory and there is a maximum bandwidth removing data within a CPU boardand from board to board and there is a maximum data transfer rate to andfrom the disk drive, plus there is a finite time length required to movefrom one disk cylinder to another. In view of these considerations, thissystem operates to minimize the amount of data actually moved, itminimizes the amount of wasted buffer space, and maximizes the amount ofdata transferred to the disk at each ON position while consistent withthe size of the available buffers.

It is possible, for example, to have 28 RW heads in simultaneousoperation upon the disks doing reading and writing operations.

Memory Pool Structure: During the course of operation of the SRM, databuffers of greatly varying size are created, used and discarded. As asresult, the data buffer design provides allocation for the followingconditions so that (a) the size of the buffer memory allocated is nevermuch larger than the actual size requested so that wasted space isminimized; (b) no garbage collection operation is used which would relyon data copying since this could adversely affect system performance;(c) if there is enough free space in the memory pool to satisfy arequest, this request must not fail due to fragmentation; (d) theallocation must be done efficiently both during allocation of space andde-allocation of space.

With this consideration, the memory pool is partitioned intoone-kilobyte physical buffer blocks. A bit map is used to keep track ofthe allocated and the free buffer blocks and all the buffers will beorganized as Data Chain Blocks as defined in the RMX 286 system. Thisinsures that the average wasted space will be 512 bytes per buffer butthat the data buffers will be consistent with those used by RMX 286buffer pools.

Data Buffer Object: In order to reduce the amount of data copying, whilestill retaining the flexibility of a memory pool composed of many smallphysical buffer blocks, a concept was devised of a "Data Buffer Object".A Data Buffer Object describes a (logical) data buffer of a specificsize. It has an associated Data Block, within which resides the actualdata buffer. This permits reference to various portions of a large blockof data without actually moving the data involved to its own buffer.Since all of the file management routines accept Data Buffer Objects asparameters, this permits actual data copying to be significantlyreduced.

The Data Buffer Object is described by a data buffer object descriptorwhich provides the parameters and information required to describe theData Buffer Object. The Data Buffer Object contains an area of privatefields which are manipulated by the user of the Data Buffer Object tostore information associated with the data contained in the Data ChainBlocks or the buffer area.

A Logical Data Block can be either: (a) contiguous buffer area inmemory, or (b) Data Chain Block which points in turn to many physicaldata blocks similar to the RMX system.

Since the described Data Chain Block is identical to the RMX data chainblock, they can be used directly when sending or receiving data with themessage-passing mechanisms.

FIGS. 14A through 14D are schematic drawings illustrating therelationships between index files (for the RMX software system) inrelationship to the physically structured data files and the logicallystructured files.

The Structured File Set (SFS) of FIG. 14A shows how the configuration(text) file on one disk area connects the index files (RMX) on anotherdisk area to the physically structured data files on another area of thedisks.

In FIG. 14B, this schematic indicates how three data files such as datafiles #1, #2, and #3 are mapped to logical records which are alsorelated to the index file n.

FIG. 14C is a schematic showing the logical structured record, where thelogical fields F1, F2, and F3 are co-related to the physical datarecords in data file #1 shown as f1, f2, and f3. Likewise, the logicalfields F4 and F5 are related to the physical fields f1 and f2 of thephysical data record in data file #2. Then the logical fields F6, F7 andF8 are related to the physical fields f1, f2, and f3 of the physicaldata record in data file #3.

FIG. 14D illustrates the physical data record shown as Record n wherebythe Record n is made up of the physical data record having a Header, afield directory area and an area for data fields. The field directoryentry for field directory area #1 shows a space for the Offset and aspace for the size information. Each one of the field directory data 1,2, 3, and 4 relates to a certain portion of the physical records datafields.

With the structured file set organization and the physical components,the storage and retrieval module is capable of storing 60 images persecond where the average check image size is a compressed image ofapproximately 20 kilobytes of data. The retrieval rate of image data fortransmission to a requesting workstation is on the order of 22 imagesper second. The disk storage structure has a minimum of two drives and amaximum of eight drives such that the minimum capacity, with two drives,is 1,600 megabytes (formatted) and the maximum capacity, with eightdrives, is 6,400 megabytes (formatted).

While the previously discussed configurations of the image and itemprocessing system shown in FIG. 1A generally involve one site andrelatively small locality area, the system is adaptable for usage in alocal-remote configuration where one portion of the system may providefor complete image and item operations with the host computer 6 but atthe same time, the host computer 6 and the local workstation andcommunications processor may be connected to distant remote locations inother cities where a completely self-sufficient remote location canprovide all the image and item processing functions without the need foran on-site host computer since the original local host computer 6 can beconnected via modems to monitor the remote operation. Since the imageand item operations do not need processing by the host computer, theremote operations can operate fully functionally and use only the hostcomputer 6 for administrative and record keeping operations which do notdiminish the high speed image and item processing operations of thesystem.

Certain prior art systems required that the host computer process allthe image data so that no image and item processing operations couldoccur without the connection of an on-site host computer. The presentlydescribed system obviates this situation since the host computer 6 ofthe present configuration does not process images and items but onlyoperates for administrative and initialization purposes plus recordkeeping purposes which do not require the high volume data streamsrequired for the image and item processing.

Thus, with reference to FIG. 15, there is seen a configuration whereby alocal site having a host computer 6 can provide fully functional imageand item processing operations through use of the local storage andretrieval module 10, the local workstation 4A, and the communicationsprocessor 4B, plus the interconnected image workstations 12.Simultaneously at a remote location such as a remote city, a documentprocessor 8_(r), a power encoder 2_(r), and a printer 14_(r) can beconnected to a modem and multiplexer unit 7_(ar). The modem-multiplexer7_(ar) is connected by long lines to the modem-multiplexer 7_(a) whichcommunicates with the host computer 6.

Likewise, the local communications processor 4B_(x) can communicate fromlocal modem 7_(b) to the remote modem 7_(br) for transmission to aremote communication processor 4B_(r) which can communicate with theremote storage and retrieval module 10_(r) and whereby remote imageworkstations 12_(r) can retrieve image and item information from thestorage/retrieval module 10_(r).

The communications processor 4B_(x) is also connected to a multiplegroup of remote storage and retrieval modules 10_(mr) which provide foradded storage and retrieval capacity for both the storage and retrievalmodule 10 at the local site and also for the storage and retrievalmodule 10_(r) at the remote site.

With reference to FIG. 9A, the storage/retrieval system operationalfunctions are shown and can be illustrated by the following examplesshown in a sequential series of steps.

The first basic operation illustrated herein is the "storage operation"on disk where enormous amounts of packet-data are received from theImage Module 8₁ (FIG. 1B). There are data packets which average 40kilobytes per check, which come across the point-to-point optical link,10_(po) to the storage retrieval system at the rate of 30 packets persecond. Thus in FIG. 9A, the IM step 101 transmits these data packets tothe step 102 (POL 10_(po) ). This data packet is pictorially representedin FIG. 9B. FIG. 9B depicts the packet of information transmittedbetween the IM (imaging module 8₁, FIG. 1B) and the storage retrievalmodule 10 for storage on magnetic disk. The IM 8₁ captures the MICR dataand image data.

Essentially there are two types of packets generated from the ImageModule 8₁ : (i) and "Image Packet" which contains a standard imageheader shown in FIG. 9C which is prefixed to the digitized image dataand (ii) a "Structured File" data packet which combines image packetswith other data necessary for storage and retrieval requirements in theSRM 10.

The Structured File packet is logically a record of a variable number ofpre-defined variable length fields. The first field (1) is a datacommunications header necessary for data integrity and transmission toan associated SRM. The second field (2) is a system header (FIS) whichfundamentally describes the remaining field in the packet. It containsfield pointers to the remaining fields. The field (3) containsinformation defined by the off-load sort program, including code linedata (MICR). The fields 4.1-4.n contain Retrieval Index numbers to beassociated with the images stored on the SRM.

Depending on the application requirements, any given image captured canbe stored in any of several different files on the SRM. Thus thecapability for, and the need to generate several RIX numbers, exists inthe image module IM 8₁. It should be noted, however, that only one copyof the image is transmitted to the SRM which subsequently, in turn, canbe copied by the SRM itself for multiple instant storage.

Finally, the Image Packets are appended to the record. These include adocument front-side image and, optionally, a document rear-side (back)image. Again referring to FIG. 9A, the Storage Processor 10_(p) operatesat step 103_(a) to queue the image data packets for subsequent writingto disk.

At step 104 of the IM services function, the Unit Processor 10_(u)transmits the packet for handling by the SRM Communication Handlerfunction, at step 105. The communication Handler routes and presents theincoming message to the SRM (via the Structured File packet) and on tothe target program on the SRM which will handle the message.

Then the Image Command Services functions at step 106, using the StorageProcessor 10_(p), in order to handle the specifics of all requests onthe SRM. These requests would include such service requests as: filemanagement, unit management, initialization, etc.

From step 106 of FIG. 9A, the image packet is split into two separatefunctional channels: (i) for sequential data to be stored, and (ii) forimage data to be stored. The "sequential data" is all non-image relateddata, and examples of such data are: text files, code files, binaryfiles, etc. The sequential data (i) is transmitted by this system filemanager function in the storage processor 10_(p), at step 107, toperform the function of file management on the SRM. This function is astandard file system/file storage and retrieval operation such ascreate, open, close, read, write, etc.

After this, the storage services function (operating in the StorageProcessor 10_(p)) at step 109, passes the sequential data to the diskdriver in step 111 and then stores the data on disk at step 112.

The second channel for image data (ii) from step 6, in Storage Processor10_(p), handles the image data for storage. Here, the image commandservices function at step 106 operates to provide commands to the ImageFile Manager function at step 108. The file manager function 108operates in the Storage Processor 10_(p).

At step 113, the Image Record Services function in Unit Processor10_(u), functions to analyze the data imbedded in the SRM messagerequesting file management services, to determine if a storage orretrieval request has been made and to transmit the image data, at step114, via the storage services function in the Storage Processor 10_(p).This functions to control the disk drive at step 111 and selects thedeposit of the image data on disk at step 112 where a selected sectoraddress is chosen. The second basic function of the SRM 10 and the SRMsubsystem involves the "retrieval" of data captured and placed on thedisks 20 (FIG. 4A).

The image command services function at step 106 can be activated by thehost 6 or workstation 12 (via workstation services 116). Thus the imagecommand services function of step 106 can operate in twochannels,--namely (i) for retrieval of sequential data, and (ii) forretrieval of image data.

For the sequential data (i), the System File Manager function at step107 (operating in the Unit Processor 10_(u) will offer the RetrievalServices function, in Unit Processor 10_(u), in step 110 which hasfunctions similar to those provided by the Image File Manager functionof step 108, and works to control the disk drive 20 via the disk driverat step 111 in order to access the designated cylinder, sector andaddress of the disk at step 112. After this, the Unit Processor 10_(u),at step 106, uses the SRM communication handler function at step 105 toactivate the workstation services function at step 116 in order totransmit to the Workstation Communication Manager in Unit Processor10_(u) at step 117, which then instructs the Ethernet Controller 10_(c)to send the requested sequential data to the workstations (12, 14, FIG.1A) at step 119, after activation of the Ethernet drivers at step 118.Thus, step 119 provides the data to the workstations as ordered from aworkstation 12 via the host 6 (FIG. 1A).

The second (ii) channel for "retrieval" in the SRM 10 module involvesthe image data retrieval at step 106 using the Image Command Servicesfunction. Here the Image Command Services of the Unit Processor 10_(u)commands the Image File Manager at step 108 in order to activate theImage Record Services at step 113, which then activates the RetrievalServices function at step 115. This commands the disk drive to access adesignated cylinder, sector and address at step 111 which will operate,at step 112, to gain data access so that the Image Command Services ofstep 106 can convey the image data to the workstations 12 via step 119.

In FIG. 9A of the Storage Retrieval Module subsystem, anotherillustration of its function would involve that of a host (6) command tothe storage/retrieval module 10. One example of this could be the "CopyCommand" where the host 6 orders that a designated packet of data ondisk 20 should be accessed and copied for storage on a second SRM moduleand its disk memory.

Here, the host 6 at step 132 (using the image record services function)transmits a copy command designating a particular image packet forcopying onto a second SRM. The host command function at step 132 and theEthernet driver function at 131 are handled by the Ethernet Controller10_(c) (4B) where the host services function at step 130 operates tohandle the host for specific services such as start/stop programs,logging and statistic generation and update, copying of structured filesand changing unit states, etc.

Thus the host services function 130 uses the SRM communication handlerfunction at step 105 and the Image Command Services function at step 106(in Unit Processor 10_(u)) in order to activate the Image File Managerfunction at step 108. This function communicates with the Image RecordServices at step 113 in order to command the retrieval services in step115 in order to control the disk drive via step 111 so as to access thedisk at step 112. The retrieval data structure for a small record sizewould involve a header, a RIX data field, and a pointer to the dataarea.

After the image data packet is accessed from the disk, then the SRM-SRMservices function at step 140 (in the Unit Processor 10_(u)) willactivate the Image Command Services function at step 106 (in UnitProcessor 10_(u)) where the packet data is handled by the SRMCommunication Handler at step 105 (also in Unit Processor 10_(u))whereupon the SRM Services function at step 140 operates on the EthernetController 10_(c) to activate the second disk drive via the driverfunction 141 and the final writing of the copied image data packet ontothe "second" storage/retrieval module via step 142.

Thus the system provides not only for the usage of a single SRM 10 butfor the intercommunication and intercooperation of multiple numbers ofstorage/retrieval modules in the system.

FIG. 16 shows a generalized block of how data from the Image CaptureModule 8₁ travels to the optical link controller 10_(po) (POL) of theStorage Retrieval Module 10 when the Storage Processor 10_(p) operatesto store data on disk unit 20 via disk controller 10_(dc). Forretrieval, the Unit Processor takes requests from workstations 12 andinitiates retrieval of requested data for transmittal to a requestingworkstation 12.

POL Controller (point-to-point optical link controller): Thepoint-to-point optical link controller 10_(po) is shown in block diagramform in FIG. 17. The POL controller is a single Multibus II board thathandles duplex serial communication at 20 megabits (Mb) per second overa pair of serial fiber optic links 9_(po). The POL controller consistsof seven major functional areas which include: the Multibus II ParallelSystem Bus (PSB) interface, the Multibus II interconnect space, theMultibus II CSM Services (central services module) functions required bythe Multibus II, the local bus extension (LBX) interface, the opticalreceiver interface, the optical transmitter interface, and the controlprocessor.

The POL controller 10_(po) has a fiber optic interface which allowsduplex communication. The hardware in the controller handles all the lowlevel communication protocol including handling errors, framing fortransmission and synchronizing the interface.

The hardware divides all messages sent into "packets" of 2,048 bytes, orless if the message or the last packet in the message is less than 2,048bytes, then generates a cyclic redundancy check (CRC) for each packet,inserts the appropriate delimiters for the packets, and then transmitsthe packets until the message is complete. The hardware can generatefour different delimiters which involve two "start" delimiters and two"end" delimiters. One start delimiter indicates the start of a messagewhile the other start delimiter is used to indicate the start of anintermediate packet. One "end" delimiter is used for terminating apacket while the other "end" delimiter is used to terminate the message.The message format is organized in the following sequence: ##STR1##where SD0 equals the starting delimiter of the entire message; ED0equals the ending limiter for the entire message;

SD1 equals the starting delimiter for an intermediate hardware frame;

ED1 equals the ending delimiter for an intermediate hardware frame;

CRC equals the cyclic redundancy check bits (16 check bits);

PACKET 1 equals the intermediate hardware frame (2,048 bytes);

PACKET n equals the remaining N bytes (mod 2,048) of the message.

The cyclic redundancy check is generated by the checker 206_(c) for eachindividual packet. The remainder of the message (mod 2048) if non-zero,must be greater than 4 bytes to ensure the correct accumulation of theCRC.

The hardware generates synchronization signals in order to insurecorrect operation of the optical link. During idle time, when there areno messages being sent, data 1's are transmitted to ensure thereceiver's clock recovery chip remains locked. During the transmissionof the message, if data is not available for transmission, thetransmitter transmits a synch signal (SYNCH 1) to keep the clockrecovery chip 203 locked, and the receiver logic active.

The receiver hardware (204_(r), FIG. 17) reassembles the hardwarepackets into the complete message while checking the individual packetsfor CRC errors. The receiver removes the sync signals (SYNCH 1) receivedand does not accumulate a CRC for them. All errors are reported at theend of the message rather than at the time detected.

In FIG. 17, the control processor CPU 226 handles all the protocolassociated with transmitting and receiving data over the fiber opticlink. The processor 226 is also responsible for handling systeminitialization of the parallel system bus interface PSB. The controlprocessor 226 ia an Intel 80286 microprocessor with EPROM and dynamicRAM for storage of data and code. It also contains two interruptcontrollers, a programmable timer, and a serial communicationscontroller for system software and diagnostics support. The Intel 80286is a microprocessor providing a 16-bit wide data path and up to 24 bitsof addressing. It can operate in one of two modes: Real Address Mode orProtected Virtual Address Mode. The address space of the 80286 consistsof memory space and I/O space. The processor allows space for up to 256interrupt vectors. The user-defined interrupts are identified via theinterrupt vector provided by the interrupt controller 208 (FIG. 17B) onthe local data bus 209 during an interrupt acknowledge cycle.

The DMA controller 228 of FIG. 17 is used to handle the message passingcoprocessor 230 and also the fiber optic transmit and receive functions.This DMA controller is designated as an advanced DMA controller (ADMA).It provides four independent DMA channels that can transfer data atrates of up to 8 megabytes per second and it supports both synchronizedand non-synchronized DMA operations with command chaining, datachaining, and other methods.

The POL controller 10_(po) uses the ADMA 228 in the mode where the ADMAsupports memory space and I/O space operations. If the CPU 226 (Intel80286) is operating in the real address mode, both the processor and theADMA can access up to one megabyte of memory space. When the processor226 operates in protected virtual address mode, both the processor andthe ADMA can access up to 16 megabytes of memory space. A board supportsblock data transfers to a maximum block length of 16 megabytes. The DMAcontroller 228 and the processor 226 share access to the local bus 209.Bus control is passed between the processor 226 and the DMA controllervia a Hold/Hold acknowledge signal handshake.

Two channels of the DMA controller 228 are configured for the messagepassing coprocessor 230 with one channel for receiving data from theparallel system bus 10_(m) and the other channel for transmitting dataover the parallel system bus 10_(m). The other two channels areconfigured for the fiber optic link with one channel for transmission ofdata and the other channel for reception of data.

The POL controller 10_(po) has a memory system which provides twomegabytes of dynamic RAM 218 and has 128 KB of EPROM 216. The DRAMparity is provided on a byte basis with a parity error causing anon-maskable interrupt to the processor 226. The refresh of the dynamicRAM is handled in hardware. The EPROM is used for the power-onconfidence testing and for initial loading of software.

The POL controller 10_(po) provides a serial I/O interface using anasynchronous RS 232 C port to allow communication with an RS 232 Ccompatible device to allow for diagnostics and software debug. Theserial interface is implemented by a Programmable CommunicationInterface chip 214 and RS 232 C drivers and receivers.

In FIG. 17, the POL controller 10_(po) provides programmable interruptcontrollers 208 to process interrupts. One is a master and the other isa slave.

A programmable interval timer 210 is provided for system softwaresupport. The preferred usage is that of an NEC 8254 programmableinterval timer which provides three 16-bit interval timers. Connected tothe data bus 209 is a static RAM/time of day clock 229. This contains2,040 bytes of static RAM, a crystal operated time of day clock, lithiumbattery and circuitry to switch power between the battery and the systempower as needed.

Several light-emitting diodes (LED's) are driven directly by hardware toprovide hardware status. Two of the LED's provide status of the parallelsystem bus interface 10_(m) while the other four LED's provide status ofthe optical interface. The optical interface status displayed shows thecondition of the transmitter and the receiver. One LED is lit toindicate the transmitter is transmitting data. One LED is lit if thecable is connected and the optical transmitter on the other side of thecable is powered up. One LED is lit if the optical receiver is notreceiving a message, and another LED is lit if the optical receiver issynchronized to the incoming data stream.

The Multibus II interface via bus 10_(m) allows communication betweenthe POL controller 10_(po) and the other controllers in thestorage/retrieval module 10. The interface to the PSB bus 10_(m)consists of the message passing coprocessor 230, the buffer transceivers233, the interconnect controller 232, and the central system serviceslogic 231. The message passing coprocessor 230 performs memory, I/Oreferences and interconnect space to the PSB interface, and handles themessage passing protocol. The message passing coprocessor 230 provides adata path between the local control processor bus 209 and the PSBinterface to bus 10_(m). The coprocessor 230 also provides access to thelocal interconnect space with a data path to the interconnect spacecontroller 232 of FIG. 17. The multibus interface includes arbitrationand transfer control, error detecting and reporting, local bus handshakecontrol, remote diagnostic testing and reporting and also boardidentification.

The POL board "interconnect space" provides a set of registers for boardconfiguration and diagnostic reporting which allows dynamicconfiguration of I/O and memory, the initiation of board diagnostics andreporting diagnostic results. This interconnect space is controlled bythe interconnect controller 232. The interconnect space functions toenable the addressing and communication to other boards connected to themultiprocessor II bus 10_(m). In the preferred embodiment, theinterconnect space of the POL controller is managed by an Intel 8751microcontroller. The Multibus II centralized system services (CSM)module 231 provides a central source for general purpose Multibus IIfunctions. These include system clock generation, system initialization,bus time out detection, and power fail handling. The POL controller10_(po) only provides these functions if the controller is located inslot zero of the Multibus II backplane. The CSM functions are performedvia 232, 230 and associated hardware.,

In FIG. 17 the optical receiver interface 200 receives serial data withan embedded clock (using Manchester encoding) over a fiber optic link.It separates the clock and recovers the data. The data is checked forframing in order to detect the "start" and the "stop" of messages. Thedata is converted to a parallel data stream and buffered in the receiverFIFO 204_(R) for later unloading by the processor ADMA 228. Using theCRC checker 206_(c), there is generated a CRC for messages in order todetect errors in transmission. The optical receiver interface consistsof the optical receiver 200, the clock recovery chip 203, the framingand sync stripping circuitry 205, the serial-to-parallel converter206_(r), the CRC 206_(c), the FIFO buffer 204_(r) and various statuscontrol registers.

The optical receiver 200 can receive non-return-zero (NRZ) data of up to50 megabits per second and can convert this to TTL levels. The POLtransfers data at 40 megabits per second. The receiver accepts 815nanometer wavelength signals.

The clock recovery circuit 203 takes the 40 megabit per secondManchester-encoded TTL signal and retimes this data to an internallygenerated 40 MHz clock, which is phase-locked onto the incoming data.The synchronization state machine 205 is used to generate the 20 MHzclock which is used to clock in the 20 megabit per second decoded data.The delimiter state machine 207 detects all delimiters sent over theinterface including start/stop and sync delimiters. This information isused by the receiver state machine (in 206_(r)) to frame the messages,load data into the FIFO's and to discard sync information. The CRCchecker 206_(c) checks the message received for errors, and reports thisat the end portion of the packets and the message. Any error is latchedin the receiver status register where it is available for the controlfirmware to read.

The receiver logic-shift register 206_(r) takes the covered data andconverts it from a serial bitstream to a parallel data stream via its16-bit shift register. The shift register accepts the 20 megahertzserial data and generates a 16-bit wide word which is used throughoutthe rest of the receiver.

The 16-bit parallel data is now loaded into the FIFO receiver buffer204_(r) to decouple the receiving of data from the unloading of thereceived data by the ADMA 228. The DMA controller 228 is hardwired toaccess the FIFO 204_(r) without providing address and therefore allowingthe DMA controller to operate in a single cycle (flyby) mode. Status andcontrol registers are provided for the receiver interface to allow thecontrol processor CPU 226 to monitor the receiver status and to controlreceiver operation. The receiver status and the control register statuscan be accessed at an I/O address "90". A read of the I/O address "90"provides input to the status register while a write to the I/O addressregister 90 writes the control register.

The optical transmitter interface of FIG. 17 receives parallel data,serializes the data, embeds a clock using Manchester encoding, thentransmits the serial data out over a fiber optic link. Messages areframed by the transmitter and the cyclic redundancy check (CRC) isgenerated for all data transmitted (via 206_(g)). The transmitter logic206_(x) sends sync information during idle time in the transmitter. Thetransmitter provides an FIFO buffer to decouple the transmission of datafrom the ADMA 228. The optical transmitter interface consists of theoptical transmitter 200_(t), the Manchester encoding circuit 206_(x),the framing and sync generation circuitry 206_(x), theparallel-to-serial converter in 206_(x), the CRC generator 206_(g), theFIFO buffer 204_(x), and status control registers which are accessed atthe I/O address "80".

The optical transmitter 200_(t) accepts a TTL signal up to 50 megahertzand converts it to an optical signal to be transmitted. In the POLcontroller, data is transferred at a 40 megabit per second rate over thetransmitter. The transmitter 200_(t) accepts 815 nanometer wavelengthsignals. The transmitter connects to a 62.5 micron fiber optic line.

The Manchester-encoding circuitry 206_(x) accepts a 20 megabit persecond serial data stream and generates a 40 megabit per secondManchester-encoded serial output containing an embedded clock signal.The transmitter interface provides circuitry to embed start/stopdelimiters for message framing. The circuit 206_(x) insertssynchronization signals into the data stream during IDLE and when datais not available for transmission. The transmitter interface generates,via 206_(g), the CRC for all messages transmitted and appends it to theends of messages. The transmitter 200_(t) receives 16-bit wide words fortransmission from the control processor 226 and converts them to aserial data stream. The conversion is done via a 16-bit shift registerin 206_(x). The output of the shift register is a 20 megabits per secondserial data stream. The transmitter FIFO buffer 204_(x) receives the16-bit parallel data in order to decouple the transmission of data fromthe loading of the data by the control processor 226. The DMA controller228 is hardwired to access the FIFO 204_(x) without providing addressand thus allowing the DMA controller to operate in a single cycle mode.Status and control registers are provided for the transmitter interfaceto allow the control processor 226 to monitor the transmitter status andto control the transmitter operation. The control and status registersare accessed at the I/O address "80".

The systems software in the POL controller 10_(po) handles the datacommunication protocol used for transmitting data over the fiber opticlink. The systems software sets up the processor 226 and the DMAcontroller 228 for transmitting and receiving data from the transmitter,the receiver and the message passing coprocessor 230. The processor 226monitors status during communication and generates the appropriatecontrol signals to initiate and terminate communication. The systemsoftware also handles the interconnect space and the initialization ofother boards which are interfaced to the parallel system bus 10_(m).

The Multibus II, seen as 10_(m) of FIG. 17, consists of the ParallelSystem Bus (often designated iPSB), a Local Bus Extension, a SerialSystem Bus, an I/O Expansion Bus, and the Multichannel DMA (directmemory access) I/O bus. The Multibus II is specified in the IEEEstandard P1296.

The Multibus II Parallel System Bus is the only bus used in thestorage/retrieval module 10. It is a high performance general purposebus that provides data movement and interprocessor communicationfunctions in addition to supporting arbitration, execution, and I/O datamovement and board configuration support. The Parallel System Bus (PSB)supports four address spaces: a 32-bit memory address space, a 16-bitI/O address space, a 32-bit message address space, and a 16-bitinterconnect address space. Data is clocked at 10 megahertz and the datacan be up to 32 bits wide.

The PSB provides for message passing. This allows two bus agents orboards to exchange information in blocks of data providing a highperformance facility for moving data from one functional module toanother without administrative overhead for memory management orsynchronization problems at the bus interface. All controller boardssupport the message passing using hardware via the message passingcoprocessor (MPC) 230. The Parallel System Bus uses message passing as amaximum burst transfer capability of 32 megabytes per second.

GLOSSARY OF ITEMS RELATING TO STORAGE/RETRIEVAL SYSTEM

BALANCING: This is the process of proving that debit and credit totalsare correct in a group of transactions.

CLUSTER: In the Image Item Processing System, this is a group ofdocument processors (with imaging capability) and the related units thatare networked together.

CODE LINE: The magnetic ink character recognition (MICR) printing thatappears at the bottom of a financial document. A document processorreads this encoding, records the code line, and passes the record on tothe item processing system for placement in the data base and for pocketselection.

DISK DRIVE: A device that reads data from a magnetic disk and copies itinto a computer's memory so that it can be used by the computer.Additionally, it is a device that writes data from the computer's memoryonto a disk so it can be stored.

DOCUMENT: This is any piece of paper relevant to the transfer ofmonetary funds and, in general, it denotes any document that can beprocessed by a document processor such as, for example, a check, adeposit ticket, or a batch control document.

DOCUMENT IDENTIFICATION NUMBER: A number assigned by the Unisys ItemProcessing System that uniquely identifies each document within a blockof work and for a given processing day. The document identificationnumber is part of the Retrieval Index (RIX), and this is endorsed oneach item as it is processed.

DOCUMENT PROCESSOR: This is a machine that reads document magnetic inkcharacter recognition (MICR) code lines and sorts the documents intopackets. Document processors can also be used to endorse, microfilm, orimage capture documents.

ENCODE: The act of printing machine-readable magnetic characters oroptical characters on a document.

ENCODER: A device that prints machine-readable magnetic characters oroptical characters of a standard size and style on a document.

FIBER OPTIC CONNECTION: A communications pathway which uses opticalfiber as its transmission media. This is used in the point-to-pointoptical link.

FIELD: This is a defined area for recording a single piece ofinformation.

FIRMWARE: A program that has been implanted in a read-only memorydevice.

FLOAT: The dollar amount of items outstanding and in the process ofcollection from banks. Float is also often designated as "uncollectedfunds".

GIGABYTE (GB): A value equivalent to one billion bytes of memory(1,000,000,000).

HOST: The mainframe computer in the Image Item Processing System thatmakes general purpose processing, storage, and communication resourcesavailable to the image application and systems programs, and alsocentralizes the monitoring and control of the system.

HOST LAN: This is the local area network controller connecting the hostto the storage and retrieval modules in the Image Item ProcessingSystem.

IMAGE: A set of digital data which represents one side of a document andwhich can be fed to a workstation screen in order to present a visualrepresentation of the document.

IMAGE BALANCING WORKSTATION: An image workstation (12) for performingbalancing in applications running on the Image Item Processing System.Here the operator views transactions to check the correctness of theitems involved, such as checking the items on a deposit slip with theactual images of the checks to be sure that they all correlate properly.

IMAGE CHECK PROCESSING SYSTEM (ICPS): An imaging application thatfacilitates amount-entry of checks, encoding of checks, code-lineidentification correction, balancing and distribution for standardover-the-counter checks.

IMAGE DATA ENTRY WORKSTATION: A workstation for performing data entry inapplications running on the Image Item Processing System.

IMAGE HEADER: A part of an image packet with information to correlatethe image data to document information stored in the host computer (6)and to allow later reconstruction of images.

IMAGE ITEM PROCESSING SYSTEM (IIPS): A Unisys product for capturing,storing and retrieving document images. This product is a platform forimaging applications, such as the Image Check Processing System, whichfacilitates financial document processing.

IMAGE PACKET: In the Image Item Processing System, a block of compressedimage data for transmission. Each packet has "header" information tocorrelate the image data to the document information stored in the hostcomputer (6). Each packet holds compressed image data.

IMAGE PRINT WORKSTATION: A workstation for printing images and textinformation relating to applications running on the Image ItemProcessing System.

IMAGE WORKSTATION: Any one of the intelligent terminals in the ImageItem Processing System which is networked to a Storage and RetrievalModule (SRM 10).

IMAGE WORKSTATION LAN: This is the local area network connecting imageworkstations 12 (FIG. 1) to the Storage/Retrieval Modules (SRM 10) inthe Image Item Processing System.

IMAGING MODULE: A part (8₁) of the document processor 8 that capturesand digitizes check images, which digitized data can be converted tooptical digitized data and transmitted via a fiber optic link to theStorage and Retrieval Module 10.

INTERCONNECT SPACE: A separate address space on Multibus II that allowsfor dynamic configuration of I/O and memory, remote diagnostic testingand reporting, and printed circuit board assembly identification.Multibus II is a trademark of the Intel Corporation of Santa Clara,Calif.

ITEM: Any piece of paper that can be processed by a document processor.Such pieces of paper will contain certain information data considered tobe of value for storage and retrieval.

ITEM PROCESSING SYSTEM: The related equipment, including computerhardware and software, for capturing information from financialdocuments (such as checks), and for using the information to performrelated tasks such as proof, correctness and balancing.

LOCAL AREA NETWORK: A data communication network confined to arelatively small area, such as a group of offices, which is usuallycapable of high speeds and heavy traffic volumes.

LOG: A record of operations of a computer system which lists each job orrun made, the time it required, the operation actions and otherpertinent and useful data.

MAGNETIC INK CHARACTER RECOGNITION (MICR): The technology of enablingprinted characters composed of a pattern of magnetic ink to be read by amachine.

MODULE: A package unit that is usually interchangeable. Modules areunits in a system which are, in turn, composed of smaller components.

NETWORK ARCHITECTURE: This involves the rules, protocols, services,formats, conventions, and interface specifications that collectivelydescribe the logical structure of a communications system and provide abasis for its design and implementation.

OPERATING SYSTEM: The software that controls the execution of computerprograms and that typically provides scheduling, debugging, input/outputcontrol, accounting, compilation, storage assignment, data management,and related services.

OPERATOR CONTROL STATION (OCS): A remote Unisys host terminal that isconnected by a direct-interconnect to the host computer 6. It is used toperform functions similar to those performed with an operator displayterminal (ODT).

OPTICAL FIBER: A thread of highly transparent glass that is pulsed veryrapidly to carry a stream of binary optical signals. In carrying a highvolume of data, the optical fibers are immune to electrical interferencethat can often plague conventional cables.

PARALLEL INTERFACE: An equipment boundary where information istransferred simultaneously over a set of paths, as, for example, whereall the data bits in a character are sent simultaneously over eightparallel paths. This is to be contrasted with a serial interface wheredata is sent serially on one path.

PIPELINE: The set of printed wiring circuit boards in the Imaging Module(8₁) that processes and compresses image data. There are two pipelinesin the system, one for front document image capture and another for reardocument image capture.

POINT-TO-POINT OPTICAL LINK: A data link that uses fiber optictechnology for images from an imaging module to a storage and retrievalmodule at the high data rates required for efficient imagingapplications.

PROTOCOL: A set of rules or conventions governing the exchange ofinformation between computer systems, or other types of electronicmodules.

REJECT POCKET: A specific pocket in the document processor sorter 8 towhich all control tickets, all items that fail the sort pattern, allitems involved in feeder exceptions, and certain specifically selecteditems selected by the sort pattern, are all sent for accumulation.

REMOTE TERMINAL: A device for communicating with a computer from sitesthat are physically separated from the computer, often distant enoughthat communications facilities, such as telephone lines, are used ratherthan direct cables.

RIX: This is the retrieval index which is a unique key used to retrieveany stored image. Elements of the "key" include the data, the locationof capture, the sorter identification, and the sequence of input.

ROM: A read-only memory used in computers which is permanentlyprogrammed with one group of frequently used instructions. It does notlose its program when the computer's power is turned off, but normallythe program cannot be changed by the user.

RS-232-C: A standard interface between data terminal equipment and datacommunication equipment (employing a 25-pin connector) in order tosupport a serial binary interchange.

SCREEN: A surface on which information is displayed, such as a videodisplay screen.

SERIAL INTERFACE: An interface on which all the data moves over the samewire one bit after the other.

SITE: A designation for document processors within a document processingcenter. If multiple document processors are used at one center, a singlephysical center can have more than one site. If only one documentprocessing data base exists, then site and center are the equivalent ofeach other. Also used to generally designate the locale or location areawhere equipment is placed.

SORT PATTERN: This is a user-defined data structure used by an inputdevice handler in order to sort documents into selected packets. Each"sort pattern" has other non-sorting parameters related to the specifictype of items being sorted.

STORAGE AND RETRIEVAL MODULE (SRM): In the Image and Item ProcessingSystem, this is the unit (SRM 10) that stores image packets on magneticdisk and sends images to image workstations (12) for display or forprinting (14).

STORAGE AND RETRIEVAL MODULE LAN: This is the local area network whichconnects storage and retrieval modules in the Image Item ProcessingSystem.

SYSTEM: In data processing, this is a collection of people, machines,and methods organized to accomplish a set of specific functions.

SYSTEM DIRECTORY: A set of records in the host computer 6 that definesthe entities in the Image Item Processing System. These recordsestablish the system configuration.

SYSTEM SERVICES: In the Image Item Processing System, these involve thecommands and supporting programming code in the system software thatform an interface between the hardware and the application software.

TERMINAL: A keyboard/display or keyboard/printer device used to inputprograms and data to the computer and to receive output from thecomputer.

THROUGHPUT: This is a measure of total system performance, usuallystated in the number of documents processed per hour of actual operationwith time for certain indirect tasks excluded.

TWO-WIRE DIRECT INTERFACE (TDI): This is a Unisys interface that isbased on the RS-232-C interface and is used for connecting peripheralsto, a host (6) through a CP 2000 communications processor (4B, FIG. 1A).

UNIT: A device having a special function. In the Image Item ProcessingSystem, this would be a basic part of the system. For example, the host6 is a unit in the system.

UTILITY PROGRAMS: These are computer programs that provide commonlyneeded services, such as transferring data from one medium to another(disk to tape) and character conversion. Utilities are designed tofacilitate or aid the operation and use of the computer for a number ofdifferent applications and uses.

WINDOW: A portion of a screen display that is dedicated to a specificuse and which can have separate documents. Each window is independentlycontrolled by the application program.

WORKSTATION: A configuration of computer equipment designed for use byone person at a time. A combination of cathode ray tube screen, centralprocessing unit, memory and keyboard with or without local storagefacilities. A workstation may be connected to a computer or may be usedas a stand-alone system for local processing.

Described herein has been a Storage/Retrieval Module apparatus workingas part of a document processing system where received documents areconverted to digital image data and stored on disk at high speeds. Ahost computer manages and administers the entire processing system sothat the image data can be retrieved and passed to one or moreworkstations for viewing and handling concurrently during execution ofimage storing operations.

While other embodiments may have similar functions to the systemdescribed herein, it should be understood that the presently developedsystem and storage retrieval capabilities are encompassed by thefollowing claims.

What is claimed is:
 1. In a bank check document handling system forcapturing image and information data of negotiated bank checks for bankrecord processing and which system is managed by a host computer, astorage/retrieval module subsystem for storing said image andinformation data for retrieval and conveyance to any one of a pluralityof image work stations and printers for conversion to human readableformat, said storage/retrieval module subsystem comprising:(a) means forreceiving digitized optical signals containing bank check document imagepackets having (i) image data and (ii) sequential non-image informationdata related to said image data; (b) means for converting said digitizedoptical signals to digitized electrical signals forming said bank checkdocument image packets; (c) storage operation means for storing, in realtime, said bank check document image packets on identified areas ofmagnetic disk units via a file management system which includes:(c1)first storage file means for storing non-image bank check document dataas a plurality of sequential files made up of a sequence of bytes ofdata; (c2) second storage file means for storing, in real time, saidbank check document image packets in a structured file system made of aplurality of records where each record has a key field with an indexidentifying each record; (d) means for retrieving, in real time, aselected bank check document image packet while simultaneous andconcurrent storing operations of bank check document image packets aretaking place, said means for retrieving including:(d1) means forselecting said first storage file means or said second storage filemeans to effectuate retrieval of either or both non-image informationand/or a selected bank check document image packet for transmission to arequesting work station or printer; (e) means for transmitting retrievedbank check document image packets to a work station or printer fordisplay; (f) means for communicating with a host computer to receiveoperational instructions and to transmit retrieved sequential non-imageinformation for use by said host computer.
 2. The storage/retrievalmodule subsystem of claim 1 wherein said file management systemincludes:(a) means to provide separate files for (i) front-of-bank checkdocument image packet (ii) back-of-bank check document image packet(iii) other identifying indicia for a bank check document.
 3. Thestorage/retrieval module subsystem of claim 1 wherein said filemanagement system includes:(a) file system services for allocation ofdisk storage areas to named files; (b) common file services to saidnamed files and to open/close said files; (c) sequential file servicesfor selecting a sequence of non-image data bank check document bytes fortransfer to a requesting work station; (d) structured file services forcreating an index to identify a specific record in a file, forsubsequent retrieval of bank check document image packets.
 4. Thestorage/retrieval module subsystem of claim 3 wherein each bank checkdocument image packet is organized with access identifiers such thatretrieval of said packet is executed after receipt of: (i) file systemname (ii) file name and (iii) said index which specifies a particularrecord in a file.
 5. The storage/retrieval module subsystem of claim 1wherein said means for receiving and said means for converting digitizedoptical signals include:(a) opto-electric controller means connected toa parallel system bus means linked to said means for storing and meansfor retrieving; (b) said parallel system bus means for linking saidmeans for receiving and converting to each of: said means for storing,said means for retrieving, said means for transmitting retrieved bankcheck document image packets, and said means for communicating with saidhost computer.
 6. The storage/retrieval module subsystem of claim 1wherein said storage operation means includes:(a) disk unit meansorganized to store 65 image packets per cylinder where each packet canaverage up to 40 kilobytes of image and related non-image informationdata.
 7. The subsystem of claim 1 wherein said storage operation meansfurther includes:(a) storage processor means for identifying andindexing each said bank check document image packet; (b) storage buffermeans for temporarily storing at least two of said bank check documentimage packets; (c) disk controller means for controlling a disk drivemeans; (d) said disk drive means for locating an addressed area of diskfor writing a packet of data, said disk drive means including:(d1) diskunit means for magnetically storing said bank check document imagepacket.
 8. The storage/retrieval module subsystem of claim 7 whereinsaid storage operation means for storing can store up to 60 of saidimage data packets per second.
 9. The storage/retrieval module subsystemof claim 7 wherein said means for retrieving includes:(a) unit processormeans for receiving requests for specifically identified non-image bankcheck document data from said bank check document image packets storedon said disk unit means and for enabling access and retrieval of saidspecifically identified non-image bank check document data, and forcommunicating completion of said access and retrieval to said hostcomputer via said means for communicating.
 10. The storage/retrievalmodule subsystem of claim 9 wherein said storage processor means, saidunit processor means and said file management system relieves said hostcomputer from storage/retrieval execution functions.
 11. Thestorage/retrieval module subsystem of claim 9 wherein said diskcontroller means includes:(a) means for receiving instructions from saidunit processor means, and for controlling an associated disk drive meansto locate an identified area of said disk unit means; (b) said diskdrive means operating to access and read from said identified area ofsaid disk unit means.
 12. The storage/retrieval module subsystem ofclaim 1 wherein said means for transmitting said retrieved bank checkdocument image packets includes:(a) a local area network controller forreceiving image data packets for transmission to a requesting workstation.
 13. The storage/retrieval module subsystem of claim 1 whereinsaid means for retrieving can retrieve, from said disk unit means, up to22 bank check document image packets per second, while said storageoperation means simultaneously executes disk unit storage operations forreceived bank check document image packets.
 14. The storage/retrievalmodule subsystem of claim 9 which includes:(a) error checking andrecovery means in each of said unit processor means, said storage buffermeans, said disk controller means, said disk drive means, and said filemanagement system.
 15. The storage/retrieval module subsystem of claim 1wherein said means for retrieving includes:(a) means for identifyingselected 40 kilobyte bank check document image packets and transmittingthem to a requesting work station at the rate of 22 packets per second.16. In a bank check handling system, controlled by a main host computer,for capturing images and non-image item data from digitized bank checkdocument image data packets being received, a storage and retrievalsubsystem for storing compressed image data of the front and back ofeach bank check document received, and for storing related non-imageitem data such as customer account number and dollar value amount foreach said received bank check document, the storage/retrieval subsystemcomprising:(a) a minimum of two disk drive means which include first andsecond disk drive units for operating first and second disk storageunits; (b) said first and second disk storage units being organized intoidentified files in a file management system; (c) first and second diskcontroller means for controlling said disk drive means; (d) a firststorage processor means for receiving said digitized bank check documentimage data packets for storage on said first and second disk storageunits in real time via said first and second disk controller means andsaid first and second disk drive means, said first storage processormeans including:(d1) first buffer memory means for temporarily storingat least two of said bank check document image data packets; (d2) a filemanagement system for;(i) filing said related non-image item data in afirst sequentially ordered file of consecutive bytes, and for (ii)filing said bank check document image packet in a second structured filemade of a plurality or records in which each record has a key field withan index identifying each record, (e) a second unit processor means forretrieving, in real time, selected non-image item data or said bankcheck document image data packets via said first and second diskcontroller means and said first and second disk drive means fortransmission to a requesting work station or printer, said second unitprocessor means including:(e1) second buffer memory means fortemporarily storing at least two bank check document image data packets;(e2) means for executing retrieval operations simultaneously andconcurrently with the execution of storage operations by said firststorage processor means; (f) optical link controller means for receivingdigitized optical signal data in digitized packets and converting saidoptical signal data to digitized electrical signals for transmission ona parallel system bus means to said first storage processor means; (g)first local area network controller means for communication between aplurality of operator work stations and for facilitating data requeststo said second processor means for retrieval, and for transmittingrequested image and non-image item data to a requesting work station;(h) second local area network controller means for communicating withsaid main host computer; (i) said parallel system bus means for enablingconcurrent data exchange between said first and second processor means,said first and second disk controller means, said optical linkcontroller means, and said first and second local area networkcontroller means.